SLUSBU9D March 2014  – May 2016

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Configurations
  6. Pin Configuration and Functions
    1. 6.1Pin Descriptions
      1. 6.1.1Supply Input: BAT
      2. 6.1.2Cell Negative Connection: VSS
      3. 6.1.3Voltage Sense Node: V-
      4. 6.1.4Discharge FET Gate Drive Output: DOUT
      5. 6.1.5Charge FET Gate Drive Output: COUT
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5DC Characteristics
    6. 7.6Programmable Fault Detection Thresholds
    7. 7.7Programmable Fault Detection Timer Ranges
    8. 7.8Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1Timing Charts
    2. 8.2Test Circuits
    3. 8.3Test Circuit Diagrams
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
    4. 9.4Device Functional Modes
      1. 9.4.1Normal Operation
      2. 9.4.2Overcharge Status
      3. 9.4.3Over-Discharge Status
      4. 9.4.4Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)
      5. 9.4.5Charge Overcurrent Status
      6. 9.4.60-V Charging Function (Available)
      7. 9.4.70-V Charging Function (Unavailable)
      8. 9.4.8Delay Circuit
  10. 10Applications and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
      3. 10.2.3Application Performance Plots
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Related Links
    2. 13.2Community Resources
    3. 13.3Trademarks
    4. 13.4Electrostatic Discharge Caution
    5. 13.5Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

10 Applications and Implementation

10.1 Application Information

The bq2970 devices are a family of primary protectors used for protection of the battery pack in the application. The application drives two low-side NMOS FETs that are controlled to provide energy to the system loads or interrupt the power in the event of a fault condition.

10.2 Typical Application

bq2970 bq2971 bq2972 bq2973 SimpSchematic.gif

NOTE:

The 5-M resistor for an external gate-source is optional.
Figure 26. Typical Application Schematic, bq2970

10.2.1 Design Requirements

For this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE at TA = 25°C
Input voltage range 4.5 V to 7 V
Maximum operating discharge current7 A
Maximum Charge Current for battery pack 4.5 A
Overvoltage Protection (OVP) 4.275 V
Overvoltage detection delay timer1.2 s
Overvoltage Protection (OVP) release voltage4.175 V
Undervoltage Protection (UVP)2.8 V
Undervoltage detection delay timer150 ms
Undervoltage Protection (UVP) release voltage2.9 V
Charge Overcurrent detection (OCC) voltage–70 mV
Charge Overcurrent Detection (OCC) delay timer9 ms
Discharge Overcurrent Detection (OCD) voltage100 mV
Discharge Overcurrent Detection (OCD) delay timer18 ms
Load Short Circuit Detection SCC) voltage, BAT to –V ≤ threshold500 mV
Load Short Circuit Detection (SCC) delay timer250 µs
Load Short Circuit release voltage, BAT to –V ≥ Threshold1 V

10.2.2 Detailed Design Procedure

NOTE

The external FET selection is important to ensure the battery pack protection is sufficient and complies to the requirements of the system.

  • FET Selection: Because the maximum desired discharge current is 7 A, ensure that the Discharge Overcurrent circuit does not trigger until the discharge current is above this value.
  • The total resistance tolerated across the two external FETs (CHG + DSG) should be 100 mV/7 A = 14.3 mΩ.
  • Based on the information of the total ON resistance of the two switches, determine what would be the Charge Overcurrent Detection threshold, 14.3 mΩ × 4.5 A = 65 mV. Selecting a device with a 70-mV trigger threshold for Charge Overcurrent trigger is acceptable.
  • The total Rds ON should factor in any worst-case parameter based on the FET ON resistance, de-rating due to temperature effects and minimum required operation, and the associated gate drive (Vgs). Therefore, the FET choice should meet the following criteria:
  •     Vdss = 25 V

        Each FET Rds ON = 7.5 mΩ at Tj = 25°C and Vgs = 3.5 V

  • Imax > 50 A to allow for short Circuit Current condition for 350 µs (max delay timer). The only limiting factor during this condition is Pack Voltage/(Cell Resistance + (2 × FET_RdsON) + Trace Resistance).
  • Use the CSD16406Q3 FET for the application.
  • An RC filter is required on the BAT for noise, and enables the device to operate during sharp negative transients. The 330-Ω resistor also limits the current during a reverse connection on the system.
  • TI recommends placing a high impedance 5-MΩ across the gate source of each external FET to deplete any charge on the gate-source capacitance.

10.2.3 Application Performance Plots

bq2970 bq2971 bq2972 bq2973 1_UVP_Recovery_SLUSBU9.png
Orange Line (Channel 1) = Power Up Ramp on BAT Pin
Turquoise Line (Channel 2) = DOUT Gate Drive Output
DOUT goes from low to high when UVP Recovery = UVP Set Threshold +100 mV
Figure 27. UVP Recovery
bq2970 bq2971 bq2972 bq2973 3_Initial_Power_Up_SLUSBU9.png
Orange Line (Channel 1) = Power Up Ramp on BAT pin
Turquoise Line (Channel 2) = DOUT Gate Drive Output
Figure 29. Initial Power Up, DOUT
bq2970 bq2971 bq2972 bq2973 5_OVP_Set_Condition_SLUSBU9.png
Orange Line (Channel 1) = Power Up Ramp on BAT Pin
Turquoise Line (Channel 2) = COUT Gate Drive Output
COUT goes from high to low when OVP threshold = OVP set Threshold + set delay time
Figure 31. OVP Set Condition
bq2970 bq2971 bq2972 bq2973 2_UVP_Set_Condition_SLUSBU9.png
Orange Line (Channel 1) = Power Down Ramp on BAT Pin
Turquoise Line (Channel 2) = DOUT Date Drive Output
DOUT goes from high to low when UVP threshold = UVP set Threshold + set delay time
Figure 28. UVP Set Condition
bq2970 bq2971 bq2972 bq2973 4_Initial_Power_up_50_SLUSBU9.png
Orange Line (Channel 1) = Power Up Ramp on BAT Pin
Turquoise Line (Channel 2) = COUT Gate Drive Output
Figure 30. Initial Power Up, COUT
bq2970 bq2971 bq2972 bq2973 6_OVP_Recovery_Condition_SLUSBU9.png
Orange Line (Channel 1) = Decrease Voltage on BAT Pin
Turquoise Line (Channel 2) = COUT Gate Drive Output
COUT goes from low to high when OVP Recovery = OVP Set Threshold –100 mV
Figure 32. OVP Recovery Condition