SLUSBU9D March 2014  – May 2016

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Configurations
  6. Pin Configuration and Functions
    1. 6.1Pin Descriptions
      1. 6.1.1Supply Input: BAT
      2. 6.1.2Cell Negative Connection: VSS
      3. 6.1.3Voltage Sense Node: V-
      4. 6.1.4Discharge FET Gate Drive Output: DOUT
      5. 6.1.5Charge FET Gate Drive Output: COUT
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5DC Characteristics
    6. 7.6Programmable Fault Detection Thresholds
    7. 7.7Programmable Fault Detection Timer Ranges
    8. 7.8Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1Timing Charts
    2. 8.2Test Circuits
    3. 8.3Test Circuit Diagrams
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
    4. 9.4Device Functional Modes
      1. 9.4.1Normal Operation
      2. 9.4.2Overcharge Status
      3. 9.4.3Over-Discharge Status
      4. 9.4.4Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)
      5. 9.4.5Charge Overcurrent Status
      6. 9.4.60-V Charging Function (Available)
      7. 9.4.70-V Charging Function (Unavailable)
      8. 9.4.8Delay Circuit
  10. 10Applications and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
      3. 10.2.3Application Performance Plots
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Related Links
    2. 13.2Community Resources
    3. 13.3Trademarks
    4. 13.4Electrostatic Discharge Caution
    5. 13.5Glossary
  14. 14Mechanical, Packaging, and Orderable Information

8 Parameter Measurement Information

8.1 Timing Charts

bq2970 bq2971 bq2972 bq2973 OverchargeDet.gif Figure 18. Overcharge Detection, Over-Discharge Detection
bq2970 bq2971 bq2972 bq2973 DischargeOver.gif Figure 19. Discharge Overcurrent Detection

8.2 Test Circuits

The following tests are referenced as follows: The COUT and DOUT outputs are “H,” which are higher than the threshold voltage of the external logic level FETs and regarded as ON state. “L” is less than the turn ON threshold for external NMOS FETs and regarded as OFF state. The COUT pin is with respect to V–, and the DOUT pin is with respect to VSS.

  1. Overcharge detection voltage and overcharge release voltage (Test Circuit 1):
  2. The overcharge detection voltage (VOVP) is measured between the BAT and VSS pins, respectively. Once V1 is increased, the over-detection is triggered, and the delay timer expires. Then, COUT transitions from a high to low state and reduces the V1 voltage to check for the overcharge hysteresis parameter (VOVP-Hys). The delta voltage between overcharge detection voltages (VOVP) and the overcharge release occurs when the CHG FET drive output goes from low to high.

  3. Over-discharge detection voltage and over-discharge release voltage (Test Circuit 2):
  4. Over-discharge detection (VUVP) is defined as the voltage between BAT and VSS at which the DSG drive output goes from high to low by reducing the V1 voltage. V1 is set to 3.5 V and gradually reduced while V2 is set to 0 V. The over-discharge release voltage is defined as the voltage between BAT and VSS at which the DOUT drive output transition from low to high when V1 voltage is gradually increased from a VUVP condition. The overcharge hysteresis voltage is defined as the delta voltage between VUVP and the instance at which the DOUT output drive goes from low to high.

  5. Discharge overcurrent detection voltage (Test Circuit 2):
  6. The discharge overcurrent detection voltage (VOCD) is measured between V– and VSS pins and triggered when the V2 voltage is increased above VOCD threshold with respect to VSS. This delta voltage once satisfied will trigger an internal timer tOCDD before the DOUT output drive transitions from high to low.

  7. Load short circuit detection voltage (Test Circuit 2):
  8. Load short-circuit detection voltage (VSCC) is measured between V– and VSS pins and triggered when the V2 voltage is increased above VSCC threshold with respect to VSS within 10 µs. This delta voltage, once satisfied, triggers an internal timer tSCCD before the DOUT output drive transitions from high to low.

  9. Charge overcurrent detection voltage (Test Circuit 2):
  10. The charge overcurrent detection voltage (VOCC) is measured between VSS and V– pins and triggered when the V2 voltage is increased above VOCC threshold with respect to V–. This delta voltage, once satisfied, triggers an internal timer tOCCD before the COUT output drive transitions from high to low.

  11. Operating current consumption (Test Circuit 2):
  12. The operating current consumption IBNORMAL is the current measured going into the BAT pin under the following conditions: V1 = 3.9 V and V2 = 0 V.

  13. Power down current consumption (Test Circuit 2):
  14. The operating current consumption IPower_down is the current measured going into the BAT pin under the following conditions: V1 = 1.5 V and V2 = 1.5 V.

  15. Resistance between V– and BAT pin (Test Circuit 3):
  16. Measure the resistance (RV_D) between V– and BAT pins by setting the following conditions: V1 = 1.8 V and V2 = 0 V.

  17. Current sink between V– and VSS (Test Circuit 3):
  18. Measure the current sink IV–S between V– and VSS pins by setting the following condition: V1 = 4 V.

  19. COUT current source when activated High (Test Circuit 4):
  20. Measure ICOUT current source on the COUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V, and V3 = 3.4 V.

  21. COUT current sink when activated Low (Test Circuit 4):
  22. Measure ICOUT current sink on COUT pin by setting the following conditions: V1 = 4.5 V, V2 = 0 V, and V3 = 0.5 V.

  23. DOUT current source when activated High (Test Circuit 4):
  24. Measure IDOUT current source on DOUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V, and V3 = 3.4 V.

  25. DOUT current sink when activated Low (Test Circuit 4):
  26. Measure IDOUT current sink on DOUT pin by setting the following conditions: V1 = 2.0 V, V2 = 0 V, and V3 = 0.4 V.

  27. Overcharge detection delay (Test Circuit 5):
  28. The overcharge detection delay time tOVPD is the time delay before the COUT drive output transitions from high to low once the voltage on V1 exceeds the VOVP threshold. Set V2 = 0 V and then increase V1 until BAT input exceeds the VOVP threshold, then check the time for when COUT goes from high to low.

  29. Over-discharge detection delay (Test Circuit 5):
  30. The over-discharge detection delay time tUVPD is the time delay before the DOUT drive output transitions from high to low once the voltage on V1 decreases to VUVP threshold. Set V2 = 0 V and then decrease V1 until BAT input reduces to the VUVPthreshold, then check the time of when DOUT goes from high to low.

  31. Discharge overcurrent detection delay (Test Circuit 5):
  32. The discharge overcurrent detection delay time tOCDD is the time for DOUT drive output to transition from high to low after the voltage on V2 is increased from 0 V to 0.35 V. V1 = 3.5 V and V2 starts from 0 V and increases to trigger threshold.

  33. Load short circuit detection delay (Test Circuit 5):
  34. The load short-circuit detection delay time tSCCD is the time for DOUT drive output to transition from high to low after the voltage on V2 is increased from 0 V to V1 – 1 V. V1 = 3.5 V and V2 starts from 0 V and increases to trigger threshold.

  35. Charge overcurrent detection delay (Test Circuit 5):
  36. The charge overcurrent detection delay time tOCCD is the time for COUT drive output to transition from high to low after the voltage on V2 is decreased from 0 V to –0.3 V. V1 = 3.5 V and V2 starts from 0 V and decreases to trigger threshold.

  37. 0-V battery charge starting charger voltage (Test Circuit 2):
  38. The 0-V charge for start charging voltage V0CHA is defined as the voltage between BAT and V– pins at which COUT goes high when voltage on V2 is gradually decreased from a condition of V1 = V2 = 0 V.

  39. 0-V battery charge inhibition battery voltage (Test Circuit 2):
  40. The 0-V charge inhibit for charger voltage V0INH is defined as the voltage between BAT and VSS pins at which COUT should go low as V1 is gradually decreased from V1 = 2 V and V2 = –4 V.

8.3 Test Circuit Diagrams

bq2970 bq2971 bq2972 bq2973 TestCircuit1.gif Figure 20. Test Circuit 1
bq2970 bq2971 bq2972 bq2973 TestCircuit3.gif Figure 22. Test Circuit 3
bq2970 bq2971 bq2972 bq2973 TestCircuit5.gif Figure 24. Test Circuit 5
bq2970 bq2971 bq2972 bq2973 TestCircuit2.gif Figure 21. Test Circuit 2
bq2970 bq2971 bq2972 bq2973 TestCircuit4.gif Figure 23. Test Circuit 4