SLUSBU9D March 2014  – May 2016

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Configurations
  6. Pin Configuration and Functions
    1. 6.1Pin Descriptions
      1. 6.1.1Supply Input: BAT
      2. 6.1.2Cell Negative Connection: VSS
      3. 6.1.3Voltage Sense Node: V-
      4. 6.1.4Discharge FET Gate Drive Output: DOUT
      5. 6.1.5Charge FET Gate Drive Output: COUT
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5DC Characteristics
    6. 7.6Programmable Fault Detection Thresholds
    7. 7.7Programmable Fault Detection Timer Ranges
    8. 7.8Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1Timing Charts
    2. 8.2Test Circuits
    3. 8.3Test Circuit Diagrams
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
    4. 9.4Device Functional Modes
      1. 9.4.1Normal Operation
      2. 9.4.2Overcharge Status
      3. 9.4.3Over-Discharge Status
      4. 9.4.4Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)
      5. 9.4.5Charge Overcurrent Status
      6. 9.4.60-V Charging Function (Available)
      7. 9.4.70-V Charging Function (Unavailable)
      8. 9.4.8Delay Circuit
  10. 10Applications and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
      3. 10.2.3Application Performance Plots
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Related Links
    2. 13.2Community Resources
    3. 13.3Trademarks
    4. 13.4Electrostatic Discharge Caution
    5. 13.5Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DSE Package
6-PIN WSON
Top View

Pin Functions

PINTYPEDESCRIPTION
NAMENO.
BAT5PVDD pin
COUT2OGate Drive Output for Charge FET
DOUT3OGate Drive Output for Discharge FET
NC1NCNo Connection (electrically open, do not connect to BAT or VSS)
VSS4PGround pin
V–6I/OInput pin for charger negative voltage

6.1 Pin Descriptions

6.1.1 Supply Input: BAT

This pin is the input supply for the device and is connected to the positive terminal of the battery pack. S 0.1-µF input capacitor is connected to ground for filtering noise.

6.1.2 Cell Negative Connection: VSS

This pin is an input to the device for cell negative ground reference. Internal circuits associated with cell voltage measurements and overcurrent protection input to differential amplifier for either Vds sensing or external sense resistor sensing will be referenced to this node.

6.1.3 Voltage Sense Node: V–

This is a sense node used for measuring several fault detection conditions, such as overcurrent charging or overcurrent discharging configured as Vds sensing for protection. This input, in conjunction with VSS, forms the differential measurement for the stated fault detection conditions. A 2.2-kΩ resistor is connected between this input pin and Pack– terminal of the system in the application.

6.1.4 Discharge FET Gate Drive Output: DOUT

This pin is an output to control the discharge FET. The output is driven from an internal circuitry connected to the BAT supply. This output transitions from high to low when a fault is detected, and requires the DSG FET to turn OFF. A 5-MΩ high impedance resistor is connected from DOUT to VSS for gate capacitance discharge when the FET is turned OFF.

6.1.5 Charge FET Gate Drive Output: COUT

This pin is an output to control the charge FET. The output is driven from an internal circuitry connected to the BAT supply. This output transitions from high to low when a fault is detected, and requires the CHG FET to turn OFF. A 5-MΩ high impedance resistor is connected from COUT to Pack– for gate capacitance discharge when FET is turned OFF.