SLUSBU9D March 2014 – May 2016
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
|COUT||2||O||Gate Drive Output for Charge FET|
|DOUT||3||O||Gate Drive Output for Discharge FET|
|NC||1||NC||No Connection (electrically open, do not connect to BAT or VSS)|
|V–||6||I/O||Input pin for charger negative voltage|
This pin is the input supply for the device and is connected to the positive terminal of the battery pack. S 0.1-µF input capacitor is connected to ground for filtering noise.
This pin is an input to the device for cell negative ground reference. Internal circuits associated with cell voltage measurements and overcurrent protection input to differential amplifier for either Vds sensing or external sense resistor sensing will be referenced to this node.
This is a sense node used for measuring several fault detection conditions, such as overcurrent charging or overcurrent discharging configured as Vds sensing for protection. This input, in conjunction with VSS, forms the differential measurement for the stated fault detection conditions. A 2.2-kΩ resistor is connected between this input pin and Pack– terminal of the system in the application.
This pin is an output to control the discharge FET. The output is driven from an internal circuitry connected to the BAT supply. This output transitions from high to low when a fault is detected, and requires the DSG FET to turn OFF. A 5-MΩ high impedance resistor is connected from DOUT to VSS for gate capacitance discharge when the FET is turned OFF.
This pin is an output to control the charge FET. The output is driven from an internal circuitry connected to the BAT supply. This output transitions from high to low when a fault is detected, and requires the CHG FET to turn OFF. A 5-MΩ high impedance resistor is connected from COUT to Pack– for gate capacitance discharge when FET is turned OFF.