SWRS183A June 2016  – November 2016 CC1350


  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagram - RSM Package
    2. 4.2Signal Descriptions - RSM Package
    3. 4.3Pin Diagram - RHB Package
    4. 4.4Signal Descriptions - RHB Package
    5. 4.5Pin Diagram - RGZ Package
    6. 4.6Signal Descriptions - RGZ Package
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 RF Characteristics
    6. 5.6 Receive (RX) Parameters, 861 MHz to 1054 MHz
    7. 5.7 Receive (RX) Parameters, 431 MHz to 527 MHz
    8. 5.8 Transmit (TX) Parameters, 861 MHz to 1054 MHz
    9. 5.9 Transmit (TX) Parameters, 431 MHz to 527 MHz
    10. 5.101-Mbps GFSK (Bluetooth low energy) - RX
    11. 5.111-Mbps GFSK (Bluetooth low energy) - TX
    12. 5.12PLL Parameters
    13. 5.13ADC Characteristics
    14. 5.14Temperature Sensor
    15. 5.15Battery Monitor
    16. 5.16Continuous Time Comparator
    17. 5.17Low-Power Clocked Comparator
    18. 5.18Programmable Current Source
    19. 5.19DC Characteristics
    20. 5.20Thermal Characteristics
    21. 5.21Timing and Switching Characteristics
      1. 5.21.1Reset Timing
      2. 5.21.2Switching Characteristics: Wakeup and Timing
      3. 5.21.3Clock Specifications
        1. Crystal Oscillator (XOSC_HF)
        2. Crystal Oscillator (XOSC_LF)
        3. RC Oscillator (RCOSC_HF)
        4. RC Oscillator (RCOSC_LF)
      4. 5.21.4Flash Memory Characteristics
      5. 5.21.5Synchronous Serial Interface (SSI) Characteristics
    22. 5.22Typical Characteristics
    23. 5.23Typical Characteristics - Sub-1 GHz
    24. 5.24Typical Characteristics - 2.4 GHz
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Main CPU
    3. 6.3 RF Core
    4. 6.4 Sensor Controller
    5. 6.5 Memory
    6. 6.6 Debug
    7. 6.7 Power Management
    8. 6.8 Clock Systems
    9. 6.9 General Peripherals and Modules
    10. 6.10Voltage Supply Domains
    11. 6.11System Architecture
  7. 7Application, Implementation, and Layout
    1. 7.1SimplelinkTM CC1350 LaunchPad™ Bluetooth® and Sub-1 GHz Long Range Wireless Development Kit
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Texas Instruments Low-Power RF Website
    5. 8.5 Low-Power RF eNewsletter
    6. 8.6 Additional Information
    7. 8.7 Community Resources
    8. 8.8 Trademarks
    9. 8.9 Electrostatic Discharge Caution
    10. 8.10Export Control Notice
    11. 8.11Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RSM|32
  • RGZ|48
  • RHB|32
Orderable Information

Detailed Description


Section 1.4 shows a block diagram of the core modules of the CC13xx product family.

Main CPU

The CC1350 SimpleLink Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs the application and the higher layers of the protocol stack.

The CM3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.

The CM3 features include the following:

  • 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
  • Outstanding processing performance combined with fast interrupt handling
  • ARM Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications:
    • Single-cycle multiply instruction and hardware divide
    • Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral control
    • Unaligned data access, enabling data to be efficiently packed into memory
  • Fast code execution permits slower processor clock or increases sleep mode time
  • Harvard architecture characterized by separate buses for instruction and data
  • Efficient processor core, system, and memories
  • Hardware division and fast digital-signal-processing oriented multiply accumulate
  • Saturating arithmetic for signal processing
  • Deterministic, high-performance interrupt handling for time-critical applications
  • Enhanced system debug with extensive breakpoint and trace capabilities
  • Serial wire trace reduces the number of pins required for debugging and tracing
  • Migration from the ARM7™ processor family for better performance and power efficiency
  • Optimized for single-cycle flash memory use
  • Ultra-low power consumption with integrated sleep modes
  • 1.25 DMIPS per MHz

RF Core

The RF core is a highly flexible and capable radio system that interfaces the analog RF and baseband circuits, handles data to and from the system side, and assembles the information bits in a given packet structure.

The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main CPU and leaving more resources for the user application. The RF core offers a high-level, command-based API to the main CPU.

The RF core supports a wide range of modulation formats, frequency bands, and accelerator features, which include the following (not all of the features have been characterized yet, see the CC1350 SimpleLink Wireless MCU Silicon Errata for more information):

  • Wide range of data rates:
    • From 625 bps (offering long range and high robustness) to as high as 4 Mbps
  • Wide range of modulation formats:
    • Multilevel (G) FSK and MSK
    • On-Off Keying (OOK) with optimized shaping to minimize adjacent channel leakage
    • Coding-gain support for long range
  • Dedicated packet handling accelerators:
    • Forward error correction
    • Data whitening
    • 802.15.4g mode-switch support
    • Automatic CRC
  • Automatic listen-before-talk (LBT) and clear channel assist (CCA)
  • Digital RSSI
  • Highly configurable channel filtering, supporting channel spacing schemes from 40 kHz to 4 MHz
  • High degree of flexibility, offering a future-proof solution

The RF core interfaces a highly flexible radio, with a high-performance synthesizer that can support a wide range of frequency bands.

Sensor Controller

The Sensor Controller contains circuitry that can be selectively enabled in standby mode. The peripherals in this domain may be controlled by the Sensor Controller Engine, which is a proprietary power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby significantly reducing power consumption and offloading the main CM3 CPU.

A PC-based development tool called Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces C driver source code, which the System CPU application uses to control and exchange data with the Sensor Controller. Typical use cases may be (but are not limited to) the following:

  • Analog sensors using integrated ADC
  • Digital sensors using GPIOs with bit-banged I2C or SPI
  • Capacitive sensing
  • Waveform generation
  • Pulse counting
  • Key scan
  • Quadrature decoder for polling rotational sensors

The peripherals in the Sensor Controller include the following:

  • The low-power clocked comparator can be used to wake the device from any state in which the comparator is active. A configurable internal reference can be used with the comparator. The output of the comparator can also be used to trigger an interrupt or the ADC.
  • Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital converter, and a comparator. The continuous time comparator in this block can also be used as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline tracking, hysteresis, filtering, and other related functions.
  • The ADC is a 12-bit, 200-ksamples/s ADC with 8 inputs and a built-in voltage reference. The ADC can be triggered by many different sources, including timers, I/O pins, software, the analog comparator, and the RTC.
  • The analog modules can be connected to up to eight different GPIOs (see Table 6-1).

The peripherals in the Sensor Controller can also be controlled from the main application processor.

Table 6-1 GPIOs Connected to the Sensor Controller(1)

7 × 7 RGZ
5 × 5 RHB
4 × 4 RSM
Depending on the package size, up to 15 pins can be connected to the Sensor Controller. Up to eight of these pins can be connected to analog modules.


The flash memory provides nonvolatile storage for code and data. The flash memory is in-system programmable.

The SRAM (static RAM) is split into two 4-KB blocks and two 6-KB blocks and can be used to store data and execute code. Retention of the RAM contents in standby mode can be enabled or disabled individually for each block to minimize power consumption. In addition, if flash cache is disabled, the 8-KB cache can be used as general-purpose RAM.

The ROM provides preprogrammed, embedded TI-RTOS kernel and Driverlib. The ROM also contains a bootloader that can be used to reprogram the device using SPI or UART.


The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.

Power Management

To minimize power consumption, the CC1350 device supports a number of power modes and power-management features (see Table 6-2).

Table 6-2 Power Modes

Supply SystemOnOnDuty CycledOffOff
Current1.2 mA + 25.5 µA/MHz570 µA0.6 µA185 nA0.1 µA
Wake-up Time to CPU Active(1)14 µs174 µs1015 µs1015 µs
Register RetentionFullFullPartialNoNo
SRAM RetentionFullFullFullNoNo
High-Speed ClockXOSC_HF or
Low-Speed ClockXOSC_LF or
Sensor ControllerAvailableAvailableAvailableOffOff
Wake-up on RTCAvailableAvailableAvailableOffOff
Wake-up on Pin EdgeAvailableAvailableAvailableAvailableOff
Wake-up on Reset PinAvailableAvailableAvailableAvailableAvailable
Brown Out Detector (BOD)ActiveActiveDuty CycledOffN/A
Power On Reset (POR)ActiveActiveActiveActiveN/A
Not including RTOS overhead

In active mode, the application CM3 CPU is actively executing code. Active mode provides normal operation of the processor and all of the peripherals that are currently enabled. The system clock can be any available clock source (see Table 6-2).

In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked and no code is executed. Any interrupt event returns the processor to active mode.

In standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor Controller event is required to return the device to active mode. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode.

In shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or POR by reading the reset status register. The only state retained in this mode is the latched I/O state and the flash memory contents.

The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller independent of the main CPU. This means that the main CPU does not have to wake up, for example to execute an ADC sample or poll a digital sensor over SPI, thus saving both current and wake-up time that would otherwise be wasted. The Sensor Controller Studio lets the user configure the Sensor Controller and choose which peripherals are controlled and which conditions wake up the main CPU.

Clock Systems

The CC1350 device supports two external and two internal clock sources.

A 24-MHz external crystal is required as the frequency reference for the radio. This signal is doubled internally to create a 48-MHz clock.

The 32.768-kHz crystal is optional. The low-speed crystal oscillator is designed for use with a 32.768-kHz watch-type crystal.

The internal high-speed RC oscillator (48-MHz) can be used as a clock source for the CPU subsystem.

The internal low-speed RC oscillator (32-kHz) can be used as a reference if the low-power crystal oscillator is not used.

The 32-kHz clock source can be used as external clocking reference through GPIO.

General Peripherals and Modules

The I/O controller controls the digital I/O pins and contains multiplexer circuitry to assign a set of peripherals to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge (configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs have high-drive capabilities, which are marked in bold in Section 4.

The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz.

The UART implements a universal asynchronous receiver and transmitter function. The UART supports flexible baud-rate generation up to a maximum of 3 Mbps.

Timer 0 is a general-purpose timer module (GPTM) that provides two 16-bit timers. The GPTM can be configured to operate as a single 32-bit timer, dual 16-bit timers, or as a PWM module.

Timer 1, Timer 2, and Timer 3 are also GPTMs; each timer is functionally equivalent to Timer 0.

In addition to these four timers, a separate timer in the RF core handles timing for RF protocols; the RF timer can be synchronized to the RTC.

The I2S interface is used to handle digital audio (for more information, see the CC13xx, CC26xx SimpleLink™ Wireless MCU Technical Reference Manual).

The I2C interface is used to communicate with devices compatible with the I2C standard. The I2C interface can handle 100-kHz and 400-kHz operation, and can serve as both I2C master and I2C slave.

The TRNG module provides a true, nondeterministic noise source for the purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.

The watchdog timer is used to regain control if the system fails due to a software error after an external device fails to respond as expected. The watchdog timer can generate an interrupt or a reset when a predefined time-out value is reached.

The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the CM3 CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data.

Some features of the µDMA controller follow (this is not an exhaustive list):

  • Highly flexible and configurable channel operation of up to 32 channels
  • Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral
  • Data sizes of 8, 16, and 32 bits

The AON domain contains circuitry that is always enabled, except when in shutdown mode (where the digital supply is off). This circuitry includes the following:

  • The RTC can be used to wake the device from any state where it is active. The RTC contains three compare registers and one capture register. With software support, the RTC can be used for clock and calendar operation. The RTC is clocked from the 32-kHz RC oscillator or crystal. The RTC can also be compensated to tick at the correct frequency even when the internal 32-kHz RC oscillator is used instead of a crystal.
  • The battery monitor and temperature sensor are accessible by software and provide a battery status indication as well as a coarse temperature measure.

Voltage Supply Domains

The CC1350 device can interface to two or three different voltage domains depending on the package type. On-chip level converters ensure correct operation as long as the signal voltage on each input/output pin is set with respect to the corresponding supply pin (VDDS, VDDS2, or VDDS3). Table 6-3 lists the pin-to-VDDS mapping.

Table 6-3 Pin Function to VDDS Mapping Table

VQFN 7 × 7 (RGZ)VQFN 5 × 5 (RHB)VQFN 4 × 4 (RSM)
VDDS(1)DIO 23–30
DIO 7–14
DIO 5–9
VDDS2DIO 1–11DIO 0–6
DIO 0–4
VDDS3DIO 12–22
The VDDS_DCDC pin must always be connected to the same voltage as the VDDS pin.

System Architecture

Depending on the product configuration, the CC1350 device can function as a wireless network processor (WNP – a device running the wireless protocol stack, with the application running on a separate host MCU), or as a system-on-chip (SoC) with the application and protocol stack running on the ARM CM3 core inside the device.

In the first case, the external host MCU communicates with the device using SPI or UART. In the second case, the application must be written according to the application framework supplied with the wireless protocol stack.