SWRS183A June 2016 – November 2016 CC1350
Section 1.4 shows a block diagram of the core modules of the CC13xx product family.
The CC1350 SimpleLink Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs the application and the higher layers of the protocol stack.
The CM3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
The CM3 features include the following:
The RF core is a highly flexible and capable radio system that interfaces the analog RF and baseband circuits, handles data to and from the system side, and assembles the information bits in a given packet structure.
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main CPU and leaving more resources for the user application. The RF core offers a high-level, command-based API to the main CPU.
The RF core supports a wide range of modulation formats, frequency bands, and accelerator features, which include the following (not all of the features have been characterized yet, see the CC1350 SimpleLink Wireless MCU Silicon Errata for more information):
The RF core interfaces a highly flexible radio, with a high-performance synthesizer that can support a wide range of frequency bands.
The Sensor Controller contains circuitry that can be selectively enabled in standby mode. The peripherals in this domain may be controlled by the Sensor Controller Engine, which is a proprietary power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby significantly reducing power consumption and offloading the main CM3 CPU.
A PC-based development tool called Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces C driver source code, which the System CPU application uses to control and exchange data with the Sensor Controller. Typical use cases may be (but are not limited to) the following:
The peripherals in the Sensor Controller include the following:
The peripherals in the Sensor Controller can also be controlled from the main application processor.
|7 × 7 RGZ |
|5 × 5 RHB |
|4 × 4 RSM |
The flash memory provides nonvolatile storage for code and data. The flash memory is in-system programmable.
The SRAM (static RAM) is split into two 4-KB blocks and two 6-KB blocks and can be used to store data and execute code. Retention of the RAM contents in standby mode can be enabled or disabled individually for each block to minimize power consumption. In addition, if flash cache is disabled, the 8-KB cache can be used as general-purpose RAM.
The ROM provides preprogrammed, embedded TI-RTOS kernel and Driverlib. The ROM also contains a bootloader that can be used to reprogram the device using SPI or UART.
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.
To minimize power consumption, the CC1350 device supports a number of power modes and power-management features (see Table 6-2).
|MODE||SOFTWARE-CONFIGURABLE POWER MODES||RESET PIN HELD|
|Supply System||On||On||Duty Cycled||Off||Off|
|Current||1.2 mA + 25.5 µA/MHz||570 µA||0.6 µA||185 nA||0.1 µA|
|Wake-up Time to CPU Active(1)||–||14 µs||174 µs||1015 µs||1015 µs|
|High-Speed Clock||XOSC_HF or|
|XOSC_HF or |
|Low-Speed Clock||XOSC_LF or |
|XOSC_LF or |
|XOSC_LF or RCOSC_LF||Off||Off|
|Wake-up on RTC||Available||Available||Available||Off||Off|
|Wake-up on Pin Edge||Available||Available||Available||Available||Off|
|Wake-up on Reset Pin||Available||Available||Available||Available||Available|
|Brown Out Detector (BOD)||Active||Active||Duty Cycled||Off||N/A|
|Power On Reset (POR)||Active||Active||Active||Active||N/A|
In active mode, the application CM3 CPU is actively executing code. Active mode provides normal operation of the processor and all of the peripherals that are currently enabled. The system clock can be any available clock source (see Table 6-2).
In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked and no code is executed. Any interrupt event returns the processor to active mode.
In standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor Controller event is required to return the device to active mode. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode.
In shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or POR by reading the reset status register. The only state retained in this mode is the latched I/O state and the flash memory contents.
The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller independent of the main CPU. This means that the main CPU does not have to wake up, for example to execute an ADC sample or poll a digital sensor over SPI, thus saving both current and wake-up time that would otherwise be wasted. The Sensor Controller Studio lets the user configure the Sensor Controller and choose which peripherals are controlled and which conditions wake up the main CPU.
The CC1350 device supports two external and two internal clock sources.
A 24-MHz external crystal is required as the frequency reference for the radio. This signal is doubled internally to create a 48-MHz clock.
The 32.768-kHz crystal is optional. The low-speed crystal oscillator is designed for use with a 32.768-kHz watch-type crystal.
The internal high-speed RC oscillator (48-MHz) can be used as a clock source for the CPU subsystem.
The internal low-speed RC oscillator (32-kHz) can be used as a reference if the low-power crystal oscillator is not used.
The 32-kHz clock source can be used as external clocking reference through GPIO.
The I/O controller controls the digital I/O pins and contains multiplexer circuitry to assign a set of peripherals to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge (configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs have high-drive capabilities, which are marked in bold in Section 4.
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz.
The UART implements a universal asynchronous receiver and transmitter function. The UART supports flexible baud-rate generation up to a maximum of 3 Mbps.
Timer 0 is a general-purpose timer module (GPTM) that provides two 16-bit timers. The GPTM can be configured to operate as a single 32-bit timer, dual 16-bit timers, or as a PWM module.
Timer 1, Timer 2, and Timer 3 are also GPTMs; each timer is functionally equivalent to Timer 0.
In addition to these four timers, a separate timer in the RF core handles timing for RF protocols; the RF timer can be synchronized to the RTC.
The I2S interface is used to handle digital audio (for more information, see the CC13xx, CC26xx SimpleLink™ Wireless MCU Technical Reference Manual).
The I2C interface is used to communicate with devices compatible with the I2C standard. The I2C interface can handle 100-kHz and 400-kHz operation, and can serve as both I2C master and I2C slave.
The TRNG module provides a true, nondeterministic noise source for the purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
The watchdog timer is used to regain control if the system fails due to a software error after an external device fails to respond as expected. The watchdog timer can generate an interrupt or a reset when a predefined time-out value is reached.
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the CM3 CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller follow (this is not an exhaustive list):
The AON domain contains circuitry that is always enabled, except when in shutdown mode (where the digital supply is off). This circuitry includes the following:
The CC1350 device can interface to two or three different voltage domains depending on the package type. On-chip level converters ensure correct operation as long as the signal voltage on each input/output pin is set with respect to the corresponding supply pin (VDDS, VDDS2, or VDDS3). Table 6-3 lists the pin-to-VDDS mapping.
|VQFN 7 × 7 (RGZ)||VQFN 5 × 5 (RHB)||VQFN 4 × 4 (RSM)|
|VDDS2||DIO 1–11||DIO 0–6|
Depending on the product configuration, the CC1350 device can function as a wireless network processor (WNP – a device running the wireless protocol stack, with the application running on a separate host MCU), or as a system-on-chip (SoC) with the application and protocol stack running on the ARM CM3 core inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case, the application must be written according to the application framework supplied with the wireless protocol stack.