Table 4-1 Brown-Out and Black-out Voltage Levels

4.11.1 Power Supply Sequencing

For proper operation of the CC3100 device, perform the recommended power-up sequencing as follows:

1. Tie V_BAT (pins 37, 39, 44) and V_IO (pins 54 and 10) together on the board.
2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100K || 0.1 µF, RC = 10 ms).
3. For an external RTC clock, ensure that the clock is stable before RESET is deasserted (high).

For timing diagrams, see Section 4.11.2, Reset Timing.

4.11.2 Reset Timing

Figure 4-6 First-Time Power-Up and Reset Removal Timing Diagram (32K XTAL)

Table 4-2 describes the timing requirements for the 32K XTAL first-time power-up and reset removal.

4.11.2.2 nRESET (External 32K)

Figure 4-7 shows the reset timing diagram for the external 32K first-time power-up and reset removal.

Figure 4-7 First-Time Power-Up and Reset Removal Timing Diagram (External 32K)

Table 4-3 describes the timing requirements for the external 32K first-time power-up and reset removal.

Table 4-3 First-Time Power-Up and Reset Removal Timing Requirements (External 32K)

Item	Name	Description	Min	Typ	Max
T1	Supply settling time	Depends on application board power supply, decap, and so on		3 ms
T2	Hardware wakeup time			25 ms
T3	Initialization time	Firmware initialization time + radio calibration		250 ms

4.11.2.3 Wakeup from Hibernate

Figure 4-8 shows the timing diagram for wakeup from the hibernate state.

Figure 4-8 nHIB Timing Diagram

NOTE

The 32.768-kHz XTAL is kept enabled by default when the chip goes to hibernate in response to nHIB being pulled low.

Table 4-4 describes the timing requirements for nHIB.

Table 4-4 nHIB Timing Requirements

Item	Name	Description	Min	Typ	Max
Thib_min	Minimum hibernate time	Minimum pulse width of nHIB being low(2)	10 ms
Twake_from_hib	Hardware wakeup time plus firmware initialization time	See (1).		50 ms

(1) If temperature changes by more than 20°C, initialization time from HIB can increase by 200 ms due to radio calibration.

(2) Ensure that the nHIB pulse width is kept above the minimum requirement under all conditions (such as power up, MCU reset, and so on).

4.11.3 Clock Specifications

The CC3100 device requires two separate clocks for its operation:

• A slow clock running at 32.768 kHz is used for the RTC.
• A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.

The device features internal oscillators that enable the use of cheaper crystals rather than dedicated TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system and reduce overall cost.

4.11.3.1 Slow Clock Using Internal Oscillator

The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P (pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance.

Figure 4-9 shows the crystal connections for the slow clock.

Figure 4-9 RTC Crystal Connections

4.11.3.2 Slow Clock Using an External Clock

When an RTC clock oscillator is present in the system, the CC3100 device can accept this clock directly as an input. The clock is fed on the RTC_XTAL_P line and the RTC_XTAL_N line is held to VIO. The clock must be a CMOS-level clock compatible with VIO fed to the device.

Figure 4-10 shows the external RTC clock input connection.

Figure 4-10 External RTC Clock Input

4.11.3.3 Fast Clock (F_ref) Using an External Crystal

The CC3100 device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The XTAL is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading capacitors.

Figure 4-11 shows the crystal connections for the fast clock.

Figure 4-11 Fast Clock Crystal Connections

4.11.3.4 Fast Clock (F_ref) Using an External Oscillator

The CC3100 device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the system.

If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the LDO improves noise on the TCXO power supply.

Figure 4-12 shows the connection.

Figure 4-12 External TCXO Input

Table 4-5 lists the external F_ref clock requirements.

Table 4-5 External F_ref Clock Requirements (–40°C to +85°C)

Characteristics		Condition	Sym	Min	Typ	Max	Unit
Frequency					40.00		MHz
Frequency accuracy (Initial + temp + aging)						±25	ppm
Frequency input duty cycle				45	50	55	%
Clock voltage limits		Sine or clipped sine wave, AC coupled	Vpp	0.7		1.2	Vpp
Phase noise @ 40 MHz		@ 1 kHz				–125	dBc/Hz
		@ 10 kHz				–138.5	dBc/Hz
		@ 100 kHz				–143	dBc/Hz
Input impedance	Resistance			12			KΩ
	Capacitance					7	pF

4.11.4 Interfaces

This section describes the interfaces that are supported by the CC3100 device:

• Host SPI
• Flash SPI
• Host UART

4.11.4.1 Host SPI Interface Timing

Figure 4-13 Host SPI Interface Timing

Table 4-10 Host SPI Interface Timing Parameters

Parameter Number	Parameter(1)	Parameter Name	Min	Max	Unit
I1	F	Clock frequency @ VBAT = 3.3 V		20	MHz
		Clock frequency @ VBAT ≤ 2.1 V		12
I2	tclk(2)	Clock period	50		ns
I3	tLP	Clock low period		25	ns
I4	tHT	Clock high period		25	ns
I5	D	Duty cycle	45	55	%
I6	tIS	RX data setup time	4		ns
I7	tIH	RX data hold time	4		ns
I8	tOD	TX data output delay		20
I9	tOH	TX data hold time		24	ns

(1) The timing parameter has a maximum load of 20 pf at 3.3 V.

(2) Ensure that nCS (active-low signa)l is asserted 10 ns before the clock is toggled. nCS can be deasserted 10 ns after the clock edge.

4.11.4.2 Flash SPI Interface Timing

Figure 4-14 Flash SPI Interface Timing

Table 4-11 Flash SPI Interface Timing Parameters

Parameter Number	Parameter	Parameter Name	Min	Max	Unit
I1	F	Clock frequency		20	MHz
I2	tclk	Clock period	50		ns
I3	tLP	Clock low period		25	ns
I4	tHT	Clock high period		25	ns
I5	D	Duty cycle	45	55	%
I6	tIS	RX data setup time	1		ns
I7	tIH	RX data hold time	2		ns
I8	tOD	TX data output delay		8.5	ns
I9	tOH	TX data hold time		8	ns

4.12.1 SPI Flash Interface

The external serial flash stores the user profiles and firmware patch updates. The CC3100 device acts as a master in this case; the SPI serial flash acts as the slave device. This interface can work up to a speed of 20 MHz.

Figure 4-15 shows the SPI flash interface.

Figure 4-15 SPI Flash Interface

Table 4-12 lists the SPI flash interface pins.

4.12.2 SPI Host Interface

The device interfaces to an external host using the SPI interface. The CC3100 device can interrupt the host using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can work up to a speed of 20 MHz.

Figure 4-16 shows the SPI host interface.

Figure 4-16 SPI Host Interface

Table 4-13 lists the SPI host interface pins.

Table 4-14 SimpleLink UART Configuration

4.13.1 5-Wire UART Topology

Figure 4-17 shows the typical 5-wire UART topology comprised of 4 standard UART lines plus one IRQ line from the device to the host controller to allow efficient low power mode.

Figure 4-17 Typical 5-Wire UART Topology

This is the typical and recommended UART topology because it offers the maximum communication reliability and flexibility between the host and the SimpleLink device.

4.13.2 4-Wire UART Topology

The 4-wire UART topology eliminates the host IRQ line (see Figure 4-18). Using this topology requires one of the following conditions to be met:

• Host is always awake or active.
• Host goes to sleep but the UART module has receiver start-edge detection for auto wakeup and does not lose data.

Figure 4-18 4-Wire UART Configuration

4.13.3 3-Wire UART Topology

The 3-wire UART topology requires only the following lines (see Figure 4-19):

• RX
• TX
• CTS

Figure 4-19 3-Wire UART Topology

Using this topology requires one of the following conditions to be met:

• Host always stays awake or active.
• Host goes to sleep but the UART module has receiver start-edge detection for auto wakeup and does not lose data.
• Host can always receive any amount of data transmitted by the SimpleLink device because there is no flow control in this direction.

Because there is no full flow control, the host cannot stop the SimpleLink device to send its data; thus, the following parameters must be carefully considered:

• Max baud rate
• RX character interrupt latency and low-level driver jitter buffer
• Time consumed by the user's application