CD74HC4538-Q1

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Product details

Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Technology family HC Input type Standard CMOS Output type Push-Pull Supply current (µA) 80 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Retriggerable Operating temperature range (°C) -40 to 125 Rating Automotive
Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Technology family HC Input type Standard CMOS Output type Push-Pull Supply current (µA) 80 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Retriggerable Operating temperature range (°C) -40 to 125 Rating Automotive
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • Retriggerable/Resettable Capability
  • Trigger and Reset Propagation Delays Independent of RX, CX
  • Triggering From the Leading or Trailing Edge
  • Q and Q Buffered Outputs Available
  • Separate Resets
  • Wide Range of Output Pulse Widths
  • Schmitt-Trigger Input on A and B Inputs
  • Retrigger Time Is Independent of CX
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . 15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • VCC Voltage = 2 V to 6 V
  • High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V

  • Qualified for Automotive Applications
  • Retriggerable/Resettable Capability
  • Trigger and Reset Propagation Delays Independent of RX, CX
  • Triggering From the Leading or Trailing Edge
  • Q and Q Buffered Outputs Available
  • Separate Resets
  • Wide Range of Output Pulse Widths
  • Schmitt-Trigger Input on A and B Inputs
  • Retrigger Time Is Independent of CX
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . 15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • VCC Voltage = 2 V to 6 V
  • High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V

The CD74HC4538 is a dual retriggerable/resettable precision monostable multivibrator for fixed-voltage timing applications. An external resistor (RX) and external capacitor (CX) control the timing and accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of RX and CX.

Leading-edge triggering (A) and trailing-edge triggering (B) inputs are provided for triggering from either edge of the input pulse. An unused A input should be tied to GND and an unused B input should be tied to VCC. On power up, the IC is reset. Unused resets and sections must be terminated. In normal operation, the circuit retriggers on the application of each new trigger pulse. To operate in the nontriggerable mode, Q is connected to B\ when leading-edge triggering (A) is used, or Q is connected to A when trailing-edge triggering (B) is used. The period τ can be calculated from τ = (0.7) RX, CX; RMIN is 5 kΩ. CMIN is 0 pF.

The CD74HC4538 is a dual retriggerable/resettable precision monostable multivibrator for fixed-voltage timing applications. An external resistor (RX) and external capacitor (CX) control the timing and accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of RX and CX.

Leading-edge triggering (A) and trailing-edge triggering (B) inputs are provided for triggering from either edge of the input pulse. An unused A input should be tied to GND and an unused B input should be tied to VCC. On power up, the IC is reset. Unused resets and sections must be terminated. In normal operation, the circuit retriggers on the application of each new trigger pulse. To operate in the nontriggerable mode, Q is connected to B\ when leading-edge triggering (A) is used, or Q is connected to A when trailing-edge triggering (B) is used. The period τ can be calculated from τ = (0.7) RX, CX; RMIN is 5 kΩ. CMIN is 0 pF.

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Technical documentation

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Type Title Date
* Data sheet High-Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator datasheet (Rev. A) 24 Apr 2008
Application note Detect and Reset an Unresponsive Controller PDF | HTML 21 Mar 2023
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 13 Mar 2020
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

CD74HC4538-Q1 PSpice Model

SCLM120.ZIP (36 KB) - PSpice Model
Package Pins Download
SOIC (D) 16 View options
TSSOP (PW) 16 View options

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