CDC208 5V Dual 1-to-4 clock driver |

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5V Dual 1-to-4 clock driver



The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208 is characterized for operation from -40°C to 85°C.


  • Low-Skew Propagation Delay Specifications for Clock-Driver Applications
  • TTL-Compatible Inputs and CMOS-Compatible Outputs
  • Flow-Through Architecture Optimizes
    PCB Layout
  • Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-um Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (DW)

EPIC is a trademark of Texas Instruments Incorporated.


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Part number Order Function Output frequency (Max) (MHz) Number of outputs VCC out (V) VCC core (V) Operating temperature range (C) Rating Output type Package Group Package size: mm2:W x L (PKG) Input type
CDC208 Order now Single-ended     60     8     5     5     -40 to 85     Catalog     CMOS     SOIC | 20
SO | 20    
20SO: 98 mm2: 7.8 x 12.6 (SO | 20)
20SOIC: 132 mm2: 10.3 x 12.8 (SOIC | 20)