CDCLVD110A 1-to-10 LVDS clock buffer up to 1100MHz with minimum skew for clock distribution | TI.com

CDCLVD110A
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1-to-10 LVDS clock buffer up to 1100MHz with minimum skew for clock distribution

 

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Description

The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines.

When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled or disabled
(3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.

The CDCLVD110A has an improved start-up circuit that minimizes enabling time in AC- and DC-coupled systems.

The CDCLVD110A is characterized for operation from –40°C to 85°C.

Features

  • Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
  • Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
  • VCC Range: 2.5 V ±5%
  • Typical Signaling Rate Capability of Up to 1.1 GHz
  • Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
  • Full Rail-to-Rail Common-Mode Input Range
  • Receiver Input Threshold: ±100 mV
  • Available in 32-Pin LQFP and VQFN Package
  • Fail-Safe I/O-Pins for VDD = 0 V (Power Down)

Parametrics

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Part number Order Function Additive RMS jitter (Typ) (fs) Output frequency (Max) (MHz) Number of outputs VCC out (V) VCC core (V) Output skew (ps) Features Operating temperature range (C) Rating Output type Package Group Package size: mm2:W x L (PKG) Input type
CDCLVD110A Order now Differential     111     1100     10     2.5     2.5       1:10 fanout
Individual output enable control    
-40 to 85     Catalog     LVDS     LQFP | 32
VQFN | 32    
32LQFP: 49 mm2: 7 x 7 (LQFP | 32)
32VQFN: 25 mm2: 5 x 5 (VQFN | 32)    
LVDS    
CDCLVD1204 Order now Differential     171     800     4     2.5     2.5     20     2:4 fanout
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 16     16VQFN: 9 mm2: 3 x 3 (VQFN | 16)     LVCMOS
LVDS
LVPECL    
CDCLVD1208 Order now Differential     171     800     8     2.5     2.5     45     2:8 fanout
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 28     28VQFN: 25 mm2: 5 x 5 (VQFN | 28)     LVCMOS
LVDS
LVPECL    
CDCLVD1212 Order now Differential     171     800     12     2.5     2.5     35     2:12 fanout
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 40     40VQFN: 36 mm2: 6 x 6 (VQFN | 40)     LVCMOS
LVDS
LVPECL    
CDCLVD1213 Order now Differential     171     800     4     2.5     2.5     20     1:4 fanout
Selectable divider
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 16     16VQFN: 9 mm2: 3 x 3 (VQFN | 16)     LVCMOS
LVDS
LVPECL    
CDCLVD1216 Order now Differential     171     800     16     2.5     2.5     55     2:16 fanout
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     LVCMOS
LVDS
LVPECL    
CDCLVD2102 Order now Differential     171     800     4     2.5     2.5