CDCLVD1208 Low Jitter, 2-Input Selectable 1:8 Universal-to-LVDS Buffer | TI.com

CDCLVD1208
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Low Jitter, 2-Input Selectable 1:8 Universal-to-LVDS Buffer

 

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  • LMK00308  - The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.   Ultra low additive jitter,1:8 Universal Differential Buffer that can support LVDS

Description

The CDCLVD1208 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The CDCLVD1208 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1208 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1208 is packaged in small, 28-pin, 5-mm × 5-mm VQFN package.

Features

  • 2:8 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 45 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 5-mm × 5-mm, 28-Pin VQFN (RHD)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General-Purpose Clocking

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Design with CDCLVD1208

Frequency Number of Outputs
 MHz
Output Format

Parametrics

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Part number Order Function Additive RMS jitter (Typ) (fs) Output frequency (Max) (MHz) Number of outputs VCC out (V) VCC core (V) Operating temperature range (C) Rating Output type Package Group Package size: mm2:W x L (PKG) Input type
CDCLVD1208 Order now Differential     171     800     8     2.5     2.5     -40 to 85     Catalog     LVDS     VQFN | 28     28VQFN: 25 mm2: 5 x 5 (VQFN | 28)     LVCMOS
LVDS
LVPECL    
CDCLVD110A Order now Differential     111     1100     10     2.5     2.5     -40 to 85     Catalog     LVDS     LQFP | 32
VQFN | 32    
32LQFP: 49 mm2: 7 x 7 (LQFP | 32)
32VQFN: 25 mm2: 5 x 5 (VQFN | 32)    
LVDS    
CDCLVD1204 Order now Differential     171     800     4     2.5     2.5     -40 to 85     Catalog     LVDS     VQFN | 16     16VQFN: 9 mm2: 3 x 3 (VQFN | 16)     LVCMOS
LVDS
LVPECL    
CDCLVD1212 Order now Differential     171     800     12     2.5     2.5     -40 to 85     Catalog     LVDS     VQFN | 40     40VQFN: 36 mm2: 6 x 6 (VQFN | 40)     LVCMOS
LVDS
LVPECL    
CDCLVD1213 Order now Differential     171     800     4     2.5     2.5     -40 to 85     Catalog     LVDS     VQFN | 16     16VQFN: 9 mm2: 3 x 3 (VQFN | 16)     LVCMOS
LVDS
LVPECL    
CDCLVD1216 Order now Differential     171     800     16     2.5     2.5     -40 to 85     Catalog     LVDS     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     LVCMOS
LVDS
LVPECL    
CDCLVD2102 Order now Differential     171     800     4     2.5     2.5     -40 to 85     Catalog     LVDS     VQFN | 16     16VQFN: 9 mm2: 3 x 3 (VQFN | 16)     LVCMOS
LVDS
LVPECL    
CDCLVD2104 Order now Differential     171     800     8     2.5     2.5     -40 to 85     Catalog     LVDS     VQFN | 28