The CDCLVP111-SP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SP can accept two clock sources into an input multiplexer. The CDCLVP111-SP is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.
For high-speed performance, the differential mode is strongly recommended.
The CDCLVP111-SP is characterized for operation from –55°C to 125°C.
|Part number||Order||Additive RMS jitter (Typ) (fs)||Output frequency (Max) (MHz)||Input level||Number of outputs||Output level||VCC (V)||VCC out (V)||Input frequency (Max) (MHz)||Operating temperature range (C)||Rating|
||40||3500||CML, LVDS, LVPECL, SSTL||10||LVPECL||3.3||3.3||3500||
-55 to 125
25 to 25