CDCLVP1204
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
Low Jitter, 2-Input Selectable 1:4 Universal-to-LVPECL Buffer

 

Models (2)

Title Category Type Date
CDCLVPxxxx IBIS Model (Rev. B) IBIS Model ZIP 04 Oct 2013
CDCLVP1204RGT HSpice Model HSpice Model ZIP 07 Feb 2012

Design kits & evaluation modules (1)

Name Part# Type
CDCLVP1204 Evaluation Module CDCLVP1204EVM Evaluation Modules & Boards

Reference designs

SDI Video Aggregation Reference Design

This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used (...)

View the Important Notice for reference designs covering authorized use, intellectual property matters and disclaimers.

Development tools (1)

Name Part# Type
SPICE-based analog simulation program TINA-TI Circuit Design & Simulation

Design with CDCLVP1204

Frequency Number of Outputs
 MHz
Output Format