SCAS871H February   2009  – January 2016 CDCM61004

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Characteristics
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Typical Output Phase Noise CharacteristicsCorrected units for tRJIT (RMS phase jitter); changed to fs, RMS from ps, RMS
    7. 7.7  Typical Output Jitter Characteristics
    8. 7.8  Crystal Characteristics
    9. 7.9  Dissipation Ratings
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Phase-Locked Loop (PLL)
      2. 9.3.2  Configuring the PLL
      3. 9.3.3  Crystal Input Interface
      4. 9.3.4  Phase Frequency Detector (PFD)
      5. 9.3.5  Charge Pump (CP)
      6. 9.3.6  On-Chip PLL Loop Filter
      7. 9.3.7  Prescaler Divider and Feedback Divider
      8. 9.3.8  On-Chip VCO
      9. 9.3.9  LVCMOS Input Interface
      10. 9.3.10 Output Divider
      11. 9.3.11 Output Buffer
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-Up Time Estimation
      2. 10.1.2 Output Termination
      3. 10.1.3 LVPECL Termination
      4. 10.1.4 LVDS Termination
      5. 10.1.5 LVCMOS Termination
      6. 10.1.6 Interfacing Between LVPECL and HCSL
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
          1. 10.2.2.1.1 Calculation Using LCM
        2. 10.2.2.2 Device Configuration
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Considerations
    2. 11.2 Thermal Management
    3. 11.3 Power-Supply Filtering
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • One Crystal/LVCMOS Reference Input Including 24.8832 MHz, 25 MHz, and 26.5625 MHz
  • Input Frequency Range: 21.875 MHz to
    28.47 MHz
  • On-Chip VCO Operates in Frequency Range of 1.75 GHz to 2.05 GHz
  • 4x Output Available:
    • Pin-Selectable Between LVPECL, LVDS, or
      2-LVCMOS; Operates at 3.3 V
  • LVCMOS Bypass Output Available
  • Output Frequency Selectable by /1, /2, /3, /4, /6, /8 from a Single Output Divider
  • Supports Common LVPECL/LVDS Output Frequencies:
    • 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz, 150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, 187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz,
      625 MHz
  • Supports Common LVCMOS Output Frequencies:
    • 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz, 150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, 187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz
  • Output Frequency Range: 43.75 MHz to
    683.264 MHz (See Table 3)
  • Internal PLL Loop Bandwidth: 400 kHz
  • High-Performance PLL Core:
    • Phase Noise typically at –146 dBc/Hz at
      5-MHz Offset for 625-MHz LVPECL Output
    • Random Jitter typically at 0.509 ps, RMS
      ( 10 kHz to 20 MHz) for 625-MHz LVPECL Output
  • Output Duty Cycle Corrected to 50% (± 5%)
  • Low Output Skew of 30 ps on LVPECL Outputs
  • Divider Programming Using Control Pins:
    • Two Pins for Prescaler/Feedback Divider
    • Three Pins for Output Divider
    • Two Pins for Output Select
  • Chip Enable Control Pin Available
  • 3.3-V Core and I/O Power Supply
  • Industrial Temperature Range: –40°C to 85°C
  • 5-mm × 5-mm, 32-pin, VQFN (RHB) Package
  • ESD Protection Exceeds 2 kV (HBM)

2 Applications

  • Low-Jitter Clock Driver for High-End Datacom Applications Including SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
  • Cost-Effective High-Frequency Crystal Oscillator Replacement

3 Description

The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of wireline and data communication applications. The CDCM61004 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a small, 32-pin,  
5-mm × 5-mm VQFN package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCM61004 VQFN (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

CDCM61004 Block Diagram

CDCM61004 front_bd_cas871.gif

4 Revision History

Changes from G Revision (May 2011) to H Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
  • Changed input capacitance, only typical. Go
  • Added Allowable Temperature Drift for Continuous PLL Lock parameterGo
  • Changed on-chip load capacitance, only typical.Go
  • Changed parisitic to parasitic.Go
  • Added paragraph about temperature drift while locked. Go

Changes from F Revision (February 2011) to G Revision

  • Changed the On-Chip VCO sectionGo
  • Changed Figure 15Go
  • Moved the LVCMOS INPUT INTERFACE section prior to the Output Divider sectionGo

Changes from E Revision (July 2010) to F Revision

  • Changed Note 1 of the Pin Functions table From: Pullup and Pull-down see...To: Pullup refers toGo
  • Deleted RPULLDOWN from the Pin Characteristics tableGo
  • Changed the text of Configuring the PLL, deleted the last sentenceGo
  • Changed the On-Chip VCO sectionGo
  • Changed the Output Buffer sectionGo
  • Changed values in row 24.75 of Table 2Go
  • Changed the power dissipation equation From: 610.5 mW – 4 × 50 mW = 41.7 mW To: 617.1 mW – 4 × 50 mW = 417.1 mWGo
  • Deleted figure "Recommended PCB Layout for CDCM61001" from the Thermal Management section. Added text "See the mechanical data at the end of the data sheet.."Go

Changes from D Revision (February 2010) to E Revision

  • Added LVCMOS reference to first Features bulletGo
  • Added reference to LVCMOS input in DescriptionGo
  • Added reference to LVCMOS inputs in XIN parameter of Pin Functions tableGo
  • Changed name of Control Pin LVCMOS Input Characteristics section in Electrical Characteristics tableGo
  • Changed description of Crystal Input Interface sectionGo
  • Changed description of LVCMOS Input Interface sectionGo

Changes from C Revision (July 2009) to D Revision

  • Deleted references to Single-Ended and LVCMOS input throughout the documentGo
  • Deleted fIN, ΔV/ΔT, and DutyREF parameters from Electrical Characteristics tableGo
  • Added LVCMOS Input Interface sectionGo