The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication.
The CDCS504-Q1 has an output enable pin.
The device accepts a 3.3-V LVCMOS signal at the input.
The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.
By this, the device can generate output frequencies between 2 MHz and 108 MHz.
A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment.
It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package.
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|Part number||Order||Function||Number of outputs||Output frequency (Max) (MHz)||VCC core (V)||VCC out (V)||Input type||Output type||Operating temperature range (C)||Package size: mm2:W x L (PKG)||Features||Package Group||Rating|
||Clock buffer||1||108||3.3||3.3||LVCMOS||LVCMOS||-40 to 105||8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)||
|TSSOP | 8||Automotive|