SCAS951 April 2017 CDCS504-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics - Device Characteristics
    6. 6.6Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1Measurement Circuits
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
    4. 8.4Device Functional Modes
  9. Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. Design With WEBENCH® Tools
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device And Documentation Support
    1. 12.1Device Support
      1. 12.1.1Development Support
        1. Design With WEBENCH® Tools
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information


  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Part of a Family of Easy-to-Use Clock Generator Devices
  • Clock Multiplier With Selectable Output Frequency
  • Frequency Multiplication Selectable Between x1 or x4 With One External Control Pin
  • Output Disable Through Control Pin
  • Single 3.3-V Device Power Supply
  • Wide Temperature Range: –40°C to 105°C
  • Low Space Consumption 8-Pin TSSOP Package
  • Create a Custom Design Using the CDCS504-Q1 With the WEBENCH® Power Designer


    Automotive Applications Requiring Clock


The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication.

The CDCS504-Q1 has an output enable pin.

The device accepts a 3.3-V LVCMOS signal at the input.

The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.

By this, the device can generate output frequencies between 2 MHz and 108 MHz.

A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment.

It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package.

Device Information(1)

CDCS504-Q1TSSOP (8)3.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

CDCS504-Q1 bd_cas951.gif