CDCS504-Q1 (ACTIVE)

CDCS504-Q1 Clock Buffer/Clock Multiplier

CDCS504-Q1 Clock Buffer/Clock Multiplier - CDCS504-Q1
Datasheet
 

Description

The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication.

The CDCS504-Q1 has an output enable pin.

The device accepts a 3.3-V LVCMOS signal at the input.

The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.

By this, the device can generate output frequencies between 2 MHz and 108 MHz.

A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment.

It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package.

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Part of a Family of Easy-to-Use Clock Generator Devices
  • Clock Multiplier With Selectable Output Frequency
  • Frequency Multiplication Selectable Between x1 or x4 With One External Control Pin
  • Output Disable Through Control Pin
  • Single 3.3-V Device Power Supply
  • Wide Temperature Range: –40°C to 105°C
  • Low Space Consumption 8-Pin TSSOP Package
  • Create a Custom Design Using the CDCS504-Q1 With the WEBENCH® Power Designer

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Parametrics Compare all products in General Purpose

 
Input Level
Number of Outputs
Output Frequency (Max) (MHz)
Output Level
Pin/Package
Operating Temperature Range (C)
VCC Out (V)
VCC Core (V)
Programmability
CDCS504-Q1
LVCMOS   
1   
108   
LVCMOS   
8TSSOP   
-40 to 105   
3.3   
3.3   
Pin configuration   

WEBENCH® Designer CDCS504-Q1

Recommend Input Frequency Output Frequencies
 MHz
Input Frequency  MHz
 MHz  MHz