The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.
The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
|Part number||Order||Function||Output frequency (Max) (MHz)||Number of outputs||VCC core (V)||Output skew (ps)||Features||Operating temperature range (C)||Rating||Package Group||Package size: mm2:W x L (PKG)|
||Memory interface||200||4||3.3||150||SDR||-40 to 85||Catalog||
SOIC | 8
TSSOP | 8
8SOIC: 19 mm2: 3.91 x 4.9 (SOIC | 8)
8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)