SLPS667A February   2017  – July 2017 CSD17318Q2

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Characteristics
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Community Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  7. 7Mechanical Data
    1. 7.1 Q2 Package Dimensions
      1. 7.1.1 Recommended PCB Pattern
      2. 7.1.2 Recommended Stencil Pattern
    2. 7.2 Q2 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQK|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 30 V
IDSS Drain-to-source leakage VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-source leakage VDS = 0 V, VGS = 10 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 0.6 0.9 1.2 V
RDS(on) Drain-to-source on-resistance VGS = 2.5 V, ID = 8 A 20 30 mΩ
VGS = 4.5 V, ID = 8 A 13.9 16.9
VGS = 8 V, ID = 8 A 12.6 15.1
gfs Transconductance VDS = 3 V, ID = 8 A 42 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 676 879 pF
Coss Output capacitance 71 92 pF
Crss Reverse transfer capacitance 39 51 pF
RG Series gate resistance 1.0 2.0 Ω
Qg Gate charge total (4.5 V) VDS = 15 V,
ID = 8 A		 6.0 nC
Qgd Gate charge gate-to-drain 1.3 nC
Qgs Gate charge gate-to-source 1.5 nC
Qg(th) Gate charge at Vth 0.7 nC
Qoss Output charge VDS = 15 V, VGS = 0 V 2.7 nC
td(on) Turnon delay time VDS = 15 V, VGS = 4.5 V,
ID = 8 A, RG = 2 Ω		 5 ns
tr Rise time 16 ns
td(off) Turnoff delay time 13 ns
tf Fall time 4 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 8 A, VGS = 0 V 0.8 1.0 V
Qrr Reverse recovery charge VDD= 15 V, IF = 8 A,
di/dt = 300 A/μs		 2.9 nC
trr Reverse recovery time 12 ns

5.2 Thermal Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
RθJC Thermal resistance junction-to-case(1) 7.9 °C/W
RθJA Thermal resistance junction-to-ambient(1)(2) 65 °C/W
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-inch (3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.

CSD17318Q2 M0179-01_LPS260.gif
Max RθJA = 65°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu.
CSD17318Q2 M0180-01_LPS260.gif
Max RθJA = 250°C/W when mounted on a minimum pad area of 2-oz (0.071-mm) thick Cu.

5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise noted)
CSD17318Q2 D001_SLPS647.png
Figure 1. Transient Thermal Impedance
CSD17318Q2 D002_SLPS647.gif
Figure 2. Saturation Characteristics
CSD17318Q2 D003_SLPS647.gif
VDS = 5 V
Figure 3. Transfer Characteristics
CSD17318Q2 D004_SLPS647.gif
ID = 8 A VDS = 15 V
Figure 4. Gate Charge
CSD17318Q2 D006_SLPS647.gif
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
CSD17318Q2 D008_SLPS647.gif
ID = 8 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD17318Q2 D010_SLPS647.gif
Single pulse, max RθJC = 7.9°C/W
Figure 10. Maximum Safe Operating Area
CSD17318Q2 D012_SLPS647.gif
Figure 12. Maximum Drain Current vs Temperature
CSD17318Q2 D005_SLPS647.gif
Figure 5. Capacitance
CSD17318Q2 D007_SLPS647.gif
ID = 8 A
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD17318Q2 D009_SLPS647.gif
Figure 9. Typical Diode Forward Voltage
CSD17318Q2 D011_SLPS647.gif
Figure 11. Single Pulse Unclamped Inductive Switching