The CSD75207W15 device is designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery-operated space-constrained applications. The device has also been awarded with U.S. patents 7952145, 7420247, 7235845, and 6600182.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | CSD75207W15 Dual P-Channel NexFET Power MOSFET datasheet (Rev. A) | PDF | HTML | 12 Jun 2014 |
| Application note | MOSFET Support and Training Tools (Rev. D) | PDF | HTML | 09 Apr 2024 | |
| Application note | Semiconductor and IC Package Thermal Metrics (Rev. D) | PDF | HTML | 25 Mar 2024 | |
| Application note | Using MOSFET Transient Thermal Impedance Curves In Your Design | PDF | HTML | 18 Dec 2023 | |
| Application note | Solving Assembly Issues with Chip Scale Power MOSFETs | PDF | HTML | 14 Dec 2023 | |
| Application note | Using MOSFET Safe Operating Area Curves in Your Design | PDF | HTML | 13 Mar 2023 | |
| Application brief | Tips for Successfully Paralleling Power MOSFETs | PDF | HTML | 31 May 2022 | |
| More literature | WCSP Handling Guide | 07 Nov 2019 | ||
| Application note | AN-1112 DSBGA Wafer Level Chip Scale Package (Rev. AI) | 14 Jun 2019 |
For additional terms or required resources, click any title below to view the detail page where available.
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| Package | Pins | Download |
|---|---|---|
| DSBGA (YZF) | 9 | View options |
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