DAC5672A Dual-Channel, 14-Bit, 275-MSPS Digital-to-Analog Converter (DAC) | TI.com

DAC5672A (ACTIVE) Dual-Channel, 14-Bit, 275-MSPS Digital-to-Analog Converter (DAC)

 

Description

The DAC5672A device is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.

Operating with update rates of up to 275 MSPS, the DAC5672A offers exceptional dynamic performance, tight-gain, and offset matching characteristics that make the device well-suited in I/Q baseband or direct IF communication applications.

Each DAC has a high-impedance, differential-current output, suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.

The DAC5672A has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the DAC5672A supports multiplexed data for each DAC on one port when operating in the interleaved mode.

The DAC5672A is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.

The DAC5672A is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit (DAC5662) and 14-bit (DAC5672A) resolutions. Furthermore, the DAC5672A is pin compatible to the DAC2904 and AD9767 dual DACs. The device is characterized for operation over the industrial temperature range of –40°C to 85°C.

Features

  • 14-Bit Dual Transmit Digital-to-Analog Converter (DAC)
  • 275 MSPS Update Rate
  • Single-Supply: 3 V to 3.6 V
  • High Spurious-Free Dynamic Range (SFDR): 84 dBc at 5 MHz
  • High Third-Order Two-Tone Intermodulation (IMD3): 79 dBc at 15.1 MHz and 16.1 MHz
  • WCDMA Adjacent Channel Leakage Ratio (ACLR): 78 dB at Baseband
  • WCDMA ACLR: 73 dB at 30.72 MHz
  • Independent or Single Resistor Gain Control
  • Dual or Interleaved Data
  • On-Chip 1.2-V Reference
  • Low Power: 330 mW
  • Power-Down Mode: 9 mW
  • Package: 48-Pin Thin-Quad Flat Pack (TQFP)

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Parametrics

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Part number Order Sample/update rate (MSPS) Features Resolution (Bits) DAC channels Interface SFDR (dB) Supply voltage(s) (V) Power consumption (Typ) (mW) Operating temperature range (C) Package Group Package size: mm2:W x L (PKG) Rating Interpolation Architecture Output type Reference: type
DAC5672A Order now 275     Low Power     14     2     Parallel CMOS     84     3.3     330     -40 to 85     TQFP | 48     48TQFP: 81 mm2: 9 x 9 (TQFP | 48)     Catalog     1x     Current Source     Differential     Int    
DAC5652 Order now 275     Low Power     10     2     Parallel CMOS     80     3.3     290     -40 to 85     TQFP | 48     48TQFP: 81 mm2: 9 x 9 (TQFP | 48)     Catalog     1x     Current Source     Differential     Ext
Int    
DAC5652A Order now 275     Low Power     10     2     Parallel CMOS     80     3.3     290     -40 to 85     TQFP | 48
VQFN | 48    
48TQFP: 81 mm2: 9 x 9 (TQFP | 48)
48VQFN: 36 mm2: 6 x 6 (VQFN | 48)    
Catalog     1x     Current Source     Differential     Ext
Int    
DAC5662 Order now 275     Low Power     12     2     Parallel CMOS     85     3.3     330     -40 to 85     TQFP | 48     48TQFP: 81 mm2: 9 x 9 (TQFP | 48)     Catalog     1x     Current Source     Differential     Ext    
DAC5662A Order now 275     Low Power     12     2     Parallel CMOS     85     3.3     330     -40 to 85     TQFP | 48     48TQFP: 81 mm2: 9 x 9 (TQFP | 48)     Catalog     1x     Current Source     Differential     Ext    
DAC5672 Order now 275     Low Power     14     2     Parallel CMOS