DAC5682Z Dual-Channel, 16-Bit, 1.0-GSPS, 1x-4x Interpolating Digital-to-Analog Converter (DAC) | TI.com

DAC5682Z (ACTIVE)

Dual-Channel, 16-Bit, 1.0-GSPS, 1x-4x Interpolating Digital-to-Analog Converter (DAC)

Dual-Channel, 16-Bit, 1.0-GSPS, 1x-4x Interpolating Digital-to-Analog Converter (DAC) - DAC5682Z
 

Description

The DAC5682Z is a dual-channel 16-bit 1.0 GSPS DAC with wideband LVDS data input, integrated 2x/4x interpolation filters, onboard clock multiplier, and internal voltage reference. The DAC5682Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5682Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by onboard 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.

The DAC5682Z allows both complex or real output. An optional Fs/4 coarse mixer in complex mode provides coarse frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. An external RF quadrature modulator then performs the final single sideband up-conversion. The interpolation filters and complex coarse mixers efficiently provide frequency plan flexibility while enabling higher output DAC rates to simplify image rejection filtering.

The DAC5682Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin QFN package. Other single-channel members of the family include the interpolating DAC5681Z and the noninterpolating DAC5681.

Features

  • 16-Bit Digital-to-Analog Converter (DAC)
  • 1.0 GSPS Update Rate
  • 16-Bit Wideband Input LVDS Data Bus
    • 8 Sample Input FIFO
    • Interleaved I/Q Data for Dual-DAC Mode
  • High Performance
    • 73-dBc ACLR WCDMA TM1 at 180 MHz
  • 2x-32x Clock Multiplying PLL/VCO
  • 2x or 4x Interpolation Filters
    • Stopband Transition 0.4 to 0.6 Fdata
    • Filters Configurable in Either Low-Pass or High-Pass
      Mode Allows Selection of Higher Order Image
  • Fs/4 Coarse Mixer
  • On-Chip 1.2-V Reference
  • Differential Scalable Output: 2 to 20 mA
  • Package: 64-Pin 9-mm × 9-mm QFN
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

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Parametrics Compare all products in High Speed DACs (>10MSPS)

 
Sample / Update Rate (MSPS)
Features
Resolution (Bits)
DAC Channels
Interface
SFDR (dB)
Supply Voltage(s) (V)
Power Consumption (Typ) (mW)
Operating Temperature Range (C)
Package Group
Package Size: mm2:W x L (PKG)
Rating
Interpolation
Architecture
Output Type
Reference: Type
DAC5682Z DAC5681 DAC5681Z
1000     1000     1000    
Ultra High Speed     Ultra High Speed     Ultra High Speed    
16     16     16    
2     1     1    
Parallel LVDS     Parallel LVDS     Parallel LVDS    
81     81     81    
1.8,3.3     1.8, 3.3     1.8, 3.3    
1300     650     800    
-40 to 85     -40 to 85     -40 to 85    
VQFN     VQFN     VQFN    
64VQFN: 81 mm2: 9 x 9(VQFN)     64VQFN: 81 mm2: 9 x 9(VQFN)     64VQFN: 81 mm2: 9 x 9(VQFN)    
Catalog     Catalog     Catalog    
1x
2x
4x    
1x     1x
2x
4x    
Current Sink     Current Sink     Current Sink    
Differential     Differential     Differential    
Int     Int     Int