DLPS035C February 2014  – December 2016 DLPC3433 , DLPC3438


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics over Recommended Operating Conditions
    6. 6.6 Electrical Characteristics
    7. 6.7 High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8 Low-Speed SDR Electrical Characteristics
    9. 6.9 System Oscillators Timing Requirements
    10. 6.10Power-Up and Reset Timing Requirements
    11. 6.11Parallel Interface Frame Timing Requirements
    12. 6.12Parallel Interface General Timing Requirements
    13. 6.13BT656 Interface General Timing Requirements
    14. 6.14 DSI Host Timing Requirements
    15. 6.15Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1HOST_IRQ Usage Model
    2. 7.2Input Source
      1. 7.2.1Input Source - Frame Rates and 3-D Display Orientation
      2. 7.2.2Parallel Interface Supports Six Data Transfer Formats
        1. Bus - Parallel Interface Bit Mapping Modes
      3. 7.2.3DSI Interface - Supported Data Transfer Formats
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1 Interface Timing Requirements
        1. Interface
      2. 8.3.2 Display Serial Interface DSI
      3. 8.3.3 Serial Flash Interface
      4. 8.3.4 Serial Flash Programming
      5. 8.3.5 SPI Signal Routing
      6. 8.3.6 I2C Interface Performance
      7. 8.3.7 Content-Adaptive Illumination Control
      8. 8.3.8 Local Area Brightness Boost
      9. 8.3.9 3-D Glasses Operation
      10. 8.3.10DMD (Sub-LVDS) Interface
      11. 8.3.11Calibration and Debug Support
      12. 8.3.12DMD Interface Considerations
    4. 8.4Device Functional Modes
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1DLPC343x System Design Consideration
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
      3. 9.2.3Application Curve
  10. 10Power Supply Recommendations
    1. 10.1System Power-Up and Power-Down Sequence
    2. 10.2DLPC343x Power-Up Initialization Sequence
    3. 10.3DMD Fast PARK Control (PARKZ)
    4. 10.4Hot Plug Usage
    5. 10.5Maximum Signal Transition Time
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2DLPC343x Reference Clock
        1. Crystal Oscillator Configuration
          1. Layout Guidelines for DSI Interface
      3. 11.1.3General PCB Recommendations
      4. 11.1.4General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6Number of Layer Changes
      7. 11.1.7Stubs
      8. 11.1.8Terminations
      9. 11.1.9Routing Vias
    2. 11.2Layout Example
    3. 11.3Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1Device Support
      1. 12.1.1Third-Party Products Disclaimer
      2. 12.1.2Device Nomenclature
        1. Markings
      3. 12.1.3Video Timing Parameter Definitions
    2. 12.2Related Links
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information
DLPC3433 DLPC3438 OverviewDSI.jpg Figure 18. DSI - High Level View

The differential DSI Clock lane (DCLKN:DCLKP) must be in the LP11 (Idle) state upon the de-assertion of RESETZ (i.e. zero-to-one transition) and must remain in this state for a minimum of 100 µsec thereafter to ensure proper DSI initialization.

Differential Data lane '0' (DDON:DD0P) is required for DSI operation with the remaining 3 data lanes being optional / implementation specific as needed.

The state of GPIO (2:1) pins upon the de-assertion of RESETZ (i.e. a zero-to-one transition) will determine the number of DSI data lanes that will be enabled for both LP and HS bus operation.

Serial Flash Interface

DLPC343x uses an external SPI serial flash memory device for configuration support. The minimum required size is dependent on the desired minimum number of sequences, CMT tables, and splash options while the maximum supported is 16 Mb.

For access to flash, the DLPC343x uses a single SPI interface operating at a programmable frequency complying to industry standard SPI flash protocol. The programmable SPI frequency is defined to be equal to 180 MHz/N, where N is a programmable value between 5 to 127 providing a range from 36.0 to 1.41732 MHz. Note that this results in a relatively large frequency step size in the upper range (for example, 36 MHz, 30 MHz, 25.7 MHz, 22.5 MHz, and so forth) and thus this must be taken into account when choosing a flash device.

The DLPC343x supports two independent SPI chip selects; however, the flash must be connected to SPI chip select zero (SPI0_CSZ0) because the boot routine is only executed from the device connected to chip select zero (SPI0_CSZ0). The boot routine uploads program code from flash to program memory, then transfers control to an auto-initialization routine within program memory. The DLPC343x asserts the HOST_IRQ output signal high while auto-initialization is in progress, then drives it low to signal its completion to the host processor. Only after auto-initialization is complete will the DLPC343x be ready to receive commands through I2C.

The DLPC343x should support any flash device that is compatible with the modes of operation, features, and performance as defined in Table 5 and Table 6.

Table 5. SPI Flash Required Features or Modes of Operation

SPI interface widthSingle
SPI protocolSPI mode 0
Fast READ addressingAuto-incrementing
Programming modePage mode
Page size256 B
Sector size4 KB sector
Block sizeany
Block protection bits0 = Disabled
Status register bit(0)Write in progress (WIP) \{also called flash busy\}
Status register bit(1)Write enable latch (WEN)
Status register bits(6:2)A value of 0 disables programming protection
Status register bit(7)Status register write protect (SRWP)
Status register bits(15:8)
(that is expansion status byte)
The DLPC343x only supports single-byte status register R/W command execution, and thus may not be compatible with flash devices that contain an expansion status byte. However, as long as expansion status byte is considered optional in the byte 3 position and any write protection control in this expansion status byte defaults to unprotected, then the device should be compatible with DLPC343x.

To support flash devices with program protection defaults of either enabled or disabled, the DLPC343x always assumes the device default is enabled and goes through the process of disabling protection as part of the boot-up process. This process consists of:

  • A write enable (WREN) instruction executed to request write enable, followed by
  • A read status register (RDSR) instruction is then executed (repeatedly as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction is executed that writes 0 to all 8-bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC343x issues:

  • A write enable (WREN) instruction to request write enable, followed by
  • A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, the program or erase instruction is executed
  • Note the flash automatically clears the write enable status after each program and erase instruction

The specific instruction OpCode and timing compatibility requirements are listed in Table 8 and Table 7. Note however that DLPC343x does not read the flash’s electronic signature ID and thus cannot automatically adapt protocol and clock rate based on the ID.

Table 6. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements

Fast READ (1 Output)0x0BADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)(1)
Read status0x05n/an/aSTATUS(0)
Write status0x01STATUS(0) (2)
Write enable0x06
Page program0x02ADDRS(0)ADDRS(1)ADDRS(2)DATA(0)(1)
Sector erase (4KB)0x20ADDRS(0)ADDRS(1)ADDRS(2)
Chip erase0xC7
Only the first data byte is show, data continues
DLPC343x does not support access to a second/ expansion Write Status byte

The specific and timing compatibility requirements for a DLPC343x compatible flash are listed in Table 7 and Table 8.

Table 7. SPI Flash Key Timing Parameter Compatibility Requirements(1)(2)

Access frequency (all commands)FRƒC≤1.42MHz
Chip select high time (also called chip select deselect time)tSHSLtCSH≤200ns
Output hold timetCLQXtHO≥0ns
Clock low to output valid timetCLQVtV≤ 11ns
Data in set-up timetDVCHtDSU≤5ns
Data in hold timetCHDXtDH≤5ns
The timing values are related to the specification of the flash device itself, not the DLPC343x.
The DLPC343x does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins should be tied to a logic high on the PCB through an external pullup.

The DLPC343x supports 1.8-, 2.5-, or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the corresponding voltage. Table 8 contains a list of 1.8-, 2.5-, and 3.3-V compatible SPI serial flash devices supported by DLPC343x.

Table 8. DLPC343x Compatible SPI Flash Device Options(1)(2)

Yes4 MbWinbondW25Q40BWUXIG2 × 3 mm USON
Yes4 MbMacronixMX25U4033EBAI-12G1.43 × 1.94 mm WLCSP
Yes8 MbMacronixMX25U8033EBAI-12G1.68 × 1.99 mm WLCSP
Yes16 Mb Winbond W25Q16CLZPIG 5 × 6 mm WSON
The flash supply voltage must match VCC_FLSH on the DLPC343x. Special attention needs to be paid when ordering devices to be sure the desired supply voltage is attained as multiple voltage options are often available under the same base part number.
Beware when considering Numonyx (Micron) serial flash devices as they typically do not have the 4KB sector size needed to be DLPC343x compatible.
All of these flash devices appear compatible with the DLPC343x, but only those marked with yes in the DVT column have been validated on the EVM343x reference design. Those marked with no can be used at the ODM’s own risk.

Serial Flash Programming

Note that the flash can be programmed through the DLPC343x over I2C or by driving the SPI pins of the flash directly while the DLPC343x I/O are tri-stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state while power is applied to the DLPC343x. Note that SPI0_CSZ1 is not tri-stated by this same action.

SPI Signal Routing

The DLPC343x is designed to support two SPI slave devices on the SPI0 interface, specifically, a serial flash and the DLPA200x. This requires routing associated SPI signals to two locations while attempting to operate up to 36 MHz. Take special care to ensure that reflections do not compromise signal integrity. To this end, the following recommendations are provided:

  • The SPI0_CLK PCB signal trace from the DLPC343x source to each slave device should be split into separate routes as close to the DLPC343x as possible. In addition, the SPI0_CLK trace length to each device should be equal in total length.
  • The SPI0_DOUT PCB signal trace from the DLPC343x source to each slave device should be split into separate routes as close to the DLPC343x as possible. In addition, the SPI0_DOUT trace length to each device should be equal in total length(use the same strategy as SPI0_CLK).
  • The SPI0_DIN PCB signal trace from each slave device to the point where they intersect on their way back to the DLPC343x should be made equal in length and as short as possible. They should then share a common trace back to the DLPC343x.
  • SPI0_CSZ0 and SPI0_CSZ1 need no special treatment because they are dedicated signals which drive only one device.

I2C Interface Performance

Both DLPC343x I2C interface ports support 100-kHz baud rate. By definition, I2C transactions operate at the speed of the slowest device on the bus, thus there is no requirement to match the speed grade of all devices in the system.

Content-Adaptive Illumination Control

Content-adaptive illumination control (CAIC) is an image processing algorithm that takes advantage of the fact that in common real-world image content most pixels in the images are well below full scale for the for the R, G, and B digital channels being input to the DLPC343x. As a result of this the average picture level (APL) for the overall image is also well below full scale, and the system’s dynamic range for the collective set of pixel values is not fully utilized. CAIC takes advantage of this headroom between the source image APL and the top of the available dynamic range of the display system.

CAIC evaluates images frame by frame and derives three unique digital gains, one for each of the R, G, and B color channels. During CAIC image processing, each gain is applied to all pixels in the associated color channel. CAIC derives each color channel’s gain that is applied to all pixels in that channel so that the pixels as a group collectively shift upward and as close to full scale as possible. To prevent any image quality degradation, the gains are set at the point where just a few pixels in each color channel are clipped. Figure 19 and Figure 20 show an example of the application of CAIC for one color channel.

DLPC3433 DLPC3438 input_pixel_ex_LPS038.gif Figure 19. Input Pixels Example
DLPC3433 DLPC3438 display_pix_CAIC_LPS038.gif Figure 20. Displayed Pixels After CAIC Processing

Figure 20 shows the gain that is applied to a color processing channel inside the DLPC343x. CAIC will also adjust the power for the R, G, and B LED. For each color channel of an individual frame, CAIC will intelligently determine the optimal combination of digital gain and LED power. The decision regarding how much digital gain to apply to a color channel and how much to adjust the LED power for that color is heavily influenced by the software command settings sent to the DLPC343x for configuring CAIC.

As CAIC applies a digital gain to each color channel independently, and adjusts each LED’s power independently, CAIC also makes sure that the resulting color balance in the final image matches the target color balance for the projector system. Thus, the effective displayed white point of images is held constant by CAIC from frame to frame.

Since the R, G, and B channels can be gained up by CAIC inside the DLPC343x, the LED power can be turned down for any color channel until the brightness of the color on the screen is unchanged. Thus, CAIC can achieve an overall LED power reduction while maintaining the same overall image brightness as if CAIC was not used. Figure 21 shows an example of LED power reduction by CAIC for an image where the R and B LEDs can be turned down in power.

CAIC can alternatively be used to increase the overall brightness of an image while holding the total power for all LEDs constant. In summary, when CAIC is enabled CAIC can operate in one of two distinct modes:

  • Power Reduction Mode – holds overall image brightness constant while reducing LED power
  • Enhanced Brightness Mode – holds overall LED power constant while enhancing image brightness
DLPC3433 DLPC3438 CAIC_pwr_reduc_LPS038.gif Figure 21. CAIC Power Reduction Mode (for Constant Brightness)

Local Area Brightness Boost

Local area brightness boost (LABB), is an image processing algorithm that adaptively gains up regions of an image that are dim relative to the average picture level. Some regions of the image will have significant gain applied, and some regions will have little or no gain applied. LABB evaluates images frame by frame and derives the local area gains to be used uniquely for each image. Since many images have a net overall boost in gain even if some parts of the image get no gain, the overall perceived brightness of the image is boosted.

Figure 22 shows a split screen example of the impact of the LABB algorithm for an image that includes dark areas.

DLPC3433 DLPC3438 boost_bright_LPS038.gif Figure 22. Boosting Brightness in Local Areas of an Image

LABB works best when the decision about the strength of gains used is determined by ambient light conditions. For this reason, there is an option to add an ambient light sensor which can be read by the DLPC343x during each frame. Based on the sensor readings, LABB will apply higher gains for bright rooms to help overcome any washing out of images. LABB will apply lower gains in dark rooms to prevent over-punching of images.

3-D Glasses Operation

For supporting 3D glasses, the DLPC343x -based chip set outputs sync information to synchronize the Left eye/Right eye shuttering in the glasses with the displayed DMD image frames.

Two different types of glasses are often used to achieve synchronization. One relies on an IR transmitter on the system PCB to send an IR sync signal to an IR receiver in the glasses. In this case DLPC343x output signal GPIO_04 can be used to cause the IR transmitter to send an IR sync signal to the glasses. The timing for signal GPIO_04 is shown in Figure 11.

The second type of glasses relies on sync information that is encoded into the light being outputted from the projection lens. This is referred to as the DLP Link approach for 3D, and many 3D glasses from different suppliers have been built using this method. This demonstrates that the DLP Link method can work reliable. The advantage of the DLP Link approach is that it takes advantage of existing projector hardware to transmit the sync information to the glasses. This can save cost, size and power in the projector.

For generating the DLP Link sync information, one light pulse per DMD frame is outputted from the projection lens while the glasses have both shutters closed. To achieve this, the DLPC343x will tell the DLPA2000 or DLPA2005 when to turn on the illumination source (typically LEDs or lasers) so that an encoded light pulse is output once per DMD frame. Since the shutters in the glasses are both off when the DLP Link pulse is sent, the projector illumination source will also be off except for the when light is sent to create the DLP Link pulse. The timing for the light pulses for DLP Link 3D operation is shown in Figure 23 and Figure 24.

DLPC3433 DLPC3438 3D_Images.jpg Figure 23. DLPC343x L/R Frame and Signal Timing
DLPC3433 DLPC3438 3dlink_nominal_timing_table.gif
NOTE: The period between DLPLink pulses alternates between the subframe period =D and the subframe period -D, where D is the delta period.
Figure 24. 3D DLP Link Pulse Timing

DMD (Sub-LVDS) Interface

The DLPC343x ASIC DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz. The DLPC343x sub-LVDS interface supports a number of DMD display sizes, and as a function of resolution, not all output data lanes are needed as DMD display resolutions decrease in size. With internal software selection, the DLPC343x also supports a limited number of DMD interface swap configurations that can help board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 9 shows the four options available for the DLP3010 (.3 720p) DMD specifically.

Table 9. DLP3010 (.3720p) DMD – ASIC to 8-Lane DMD Pin Mapping Options

Swap Control = x0
Swap Control = x2
Input DATA_p_0
Input DATA_n_0
Input DATA_p_1
Input DATA_n_1
Input DATA_p_2
Input DATA_n_2
Input DATA_p_3
Input DATA_n_3
Input DATA_p_4
Input DATA_n_4
Input DATA_p_5
Input DATA_n_5
Input DATA_p_6
Input DATA_n_6
Input DATA_p_7
Input DATA_n_7

Calibration and Debug Support

The DLPC343x contains a test point output port, TSTPT_(7:0), which provides selected system calibration support as well as ASIC debug support. These test points are inputs while reset is applied and switch to outputs when reset is released. The state of these signals is sampled upon the release of system reset and the captured value configures the test mode until the next time reset is applied. Each test point includes an internal pulldown resistor, thus external pullups must be used to modify the default test configuration. The default configuration (x000) corresponds to the TSTPT_(7:0) outputs remaining tri-stated to reduce switching activity during normal operation. For maximum flexibility, an option to jumper to an external pullup is recommended for TSTPT_(2:0). Pullups on TSTPT_(6:3) are used to configure the ASIC for a specific mode or option. TI does not recommend adding pullups to TSTPT_(7:3) because this has adverse affects for normal operation. This external pullup is only sampled upon a 0-to-1 transition on the RESETZ input, thus changing their configuration after reset is released will not have any effect until the next time reset is asserted and released. Table 10 defines the test mode selection for one programmable scenario defined by TSTPT(2:0).

Table 10. Test Mode Selection Scenario Defined by TSTPT(2:0)(1)

TSTPT(2)HI-Z0.7 to 22.5 MHz
These are only the default output selections. Software can reprogram the selection at any time.

DMD Interface Considerations

The sub-LVDS HS interface waveform quality and timing on the DLPC343x ASIC is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

Equation 1. Setup Margin = (DLPC343x output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)
Equation 2. Hold-time Margin = (DLPC343x output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)


DLPC343x I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation is a more complicated adjustment.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided as a reference of an interconnect system that will satisfy both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.

DLPC3433 DLPC3438 stack-up_details_LPS038.gif
DMD_HS Differential SignalsDMD_LS Signals
Figure 25. DMD Interface Board Stack-Up Details

Device Functional Modes

DLPC343x has two functional modes (ON/OFF) controlled by a single pin PROJ_ON:

  • When pin PROJ_ON is set high, the projector automatically powers up and an image is projected from the DMD.
  • When pin PROJ_ON is set low, the projector automatically powers down and only microwatts of power are consumed.