DLPS029F April   2013  – May 2019 DLPC350

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. Table 1. Power and Ground Pin Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  I/O Electrical Characteristics
    6. 6.6  I2C0 and I2C1 Interface Timing Requirements
    7. 6.7  Port 1 Input Pixel Interface Timing Requirements
    8. 6.8  Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
    9. 6.9  System Oscillator Timing Requirements
    10. 6.10 Reset Timing Requirements
    11. 6.11 Video Timing Input Blanking Specification
      1. 6.11.1 Source Input Blanking
    12. 6.12 Programmable Output Clocks Switching Characteristics
    13. 6.13 DMD Interface Switching Characteristics
    14. 6.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Power Consumption
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Board Level Test Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Structured Light Applications
      2. 8.4.2 (LVDS) Receiver Supported Pixel Mapping Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Chipset Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 DLPC350 System Interfaces
            1. 9.2.1.2.1.1 Control Interface
            2. 9.2.1.2.1.2 Input Data Interface
          2. 9.2.1.2.2 DLPC350 System Output Interfaces
            1. 9.2.1.2.2.1 Illumination Interface
            2. 9.2.1.2.2.2 Trigger Interface (Sync Outputs)
          3. 9.2.1.2.3 DLPC350 System Support Interfaces
            1. 9.2.1.2.3.1 Reference Clock
            2. 9.2.1.2.3.2 PLL
            3. 9.2.1.2.3.3 Program Memory Flash Interface
          4. 9.2.1.2.4 DMD Interfaces
            1. 9.2.1.2.4.1 DLPC350 to DMD Digital Data
            2. 9.2.1.2.4.2 DLPC350 to DMD Control Interface
            3. 9.2.1.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 System Power and Reset
      1. 10.1.1 Default Conditions
        1. 10.1.1.1 1.2-V System Power
        2. 10.1.1.2 1.8-V System Power
        3. 10.1.1.3 1.9-V System Power
        4. 10.1.1.4 3.3-V System Power
        5. 10.1.1.5 FPD-Link Input LVDS System Power
      2. 10.1.2 System Power-up and Power-down Sequence
      3. 10.1.3 Power-On Sense (POSENSE) Support
      4. 10.1.4 Power-Good (PWRGOOD) Support
      5. 10.1.5 5-V Tolerant Support
      6. 10.1.6 Power Reset Operation
      7. 10.1.7 System Reset Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Video Timing Parameter Definitions
      2. 12.1.2 Device Nomenclature
      3. 12.1.3 Device Marking
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

8.1 Overview

In DLP-based solutions, image data is 100% digital from the DLPC350 input port to the image on the DMD. The image stays in digital form and is not converted into an analog signal. The DLPC350 controller processes the digital input image and converts the data into a format needed by the DMD. The DMD steers light by using binary pulse width modulation (PWM) for each micromirror. For further details, refer to DMD data sheet (TI literature number DLPS028 for the DLP4500 and DLPS032 for the DLP4500NIR).

Figure 13 is the DLPC350 controller functional block diagram. As part of the pixel processing functions, the DLPC350 controller offers format conversion functions: chroma interpolation and color-space conversion. The DLPC350 controller also offers several image-enhancement functions. The DLPC350 controller also supports the necessary functions to format the input data to the DMD. The pixel processing functions allow the DLPC350 controller and DMD to support a wide variety of resolutions including NTSC, PAL, XGA, and WXGA. The pixel processing functions can be optionally bypassed with the native 912 × 1140 pixel resolution to support direct one-to-one pixel mapping.

When accurate pattern display is needed, the native 912 × 1140 input resolution pattern has a one-to-one association with the corresponding micromirror on the DMD. The DLPC350 controller enables high-speed display of these patterns. This functionality is well-suited for techniques such as structured light, additive manufacturing, or digital exposure.

Commands can be input to the DLPC350 controller over an I2C interface.

The DLPC350 controller takes as input 24-, 27-, or 30-bit RGB data at up to 120-Hz frame rate. This frame rate is composed of three colors (red, green, and blue) with each color equally divided in the 120-Hz frame rate. Thus, each color has a 2.78-ms time slot allocated. Because each color has an 8-, 9-, or 10-bit depth, each color time slot is further divided into bit-planes. A bit-plane is the 2-dimensional arrangement of one-bit extracted from all the pixels in the full color 2D image to implement dynamic depth (see Figure 11).

DLPC350 bitslices_lps023.pngFigure 11. Bit Slices

The length of each bit-plane in the time slot is weighted by the corresponding power of two of its binary representation. This provides a binary pulse width modulation of the image. For example, a 24-bit RGB input has three colors with 8-bit depth each. Each color time slot is divided into eight bit-planes, with the sum of the weight of all bit planes in the time slot equal to 256. See Figure 12 for an illustration of this partition of the bits in a frame.

DLPC350 bitpartition_lps023.gifFigure 12. Bit Partition in a Frame for an 8-Bit Color

Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be either on or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane. With binary pulse width modulation, the intensity level of the color is reproduced by controlling the amount of time the mirror is on. For a 24-bit RGB frame image input to the DLPC350 controller, the DLPC350 controller creates 24 bit-planes, stores them in a double-buffered eDRAM embedded in the chip, and sends them to the DMD, one bit-plane at a time. Depending on the bit weight of the bit-plane, the DLPC350 controller controls the time this bit-plane is illuminated, controlling the intensity of the bit-plane. To improve image quality in video frames, these bit-planes, time slots, and color frames are shuffled and interleaved with spatial-temporal algorithms by the DLPC350 controller.