DLPS074 February 2017 DLPC4422

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Oscillators Timing Requirements
    7. 6.7 Test and Reset Timing Requirements
    8. 6.8 JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9 Port 1 Input Pixel Timing Requirements
    10. 6.10Port 3 Input Pixel Interface (via GPIO) Timing Requirements
    11. 6.11DMD LVDS Interface Timing Requirements
    12. 6.12Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13Programmable Output Clocks Switching Characteristics
    14. 6.14Synchronous Serial Port Interface (SSP) Switching Characteristics
    15. 6.15JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1System Reset Operation
        1. 7.3.1.1Power-up Reset Operation
        2. 7.3.1.2System Reset Operation
      2. 7.3.2Spread Spectrum Clock Generator Support
      3. 7.3.3GPIO Interface
      4. 7.3.4Source Input Blanking
      5. 7.3.5Video Graphics Processing Delay
      6. 7.3.6Program Memory Flash/SRAM Interface
      7. 7.3.7Calibration and Debug Support
      8. 7.3.8Board Level Test Support
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
        1. 8.2.1.1Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2Detailed Design Procedure
  9. Power Supply Recommendations
    1. 9.1System Power Regulations
    2. 9.2System Power-Up Sequence
    3. 9.3Power-On Sense (POSENSE) Support
    4. 9.4System Environment and Defaults
      1. 9.4.1DLPC4422 System Power-Up and Reset Default Conditions
      2. 9.4.21.1-V System Power
      3. 9.4.31.8-V System Power
      4. 9.4.43.3-V System Power
      5. 9.4.5Power Good (PWRGOOD) Support
      6. 9.4.65V Tolerant Support
  10. 10Layout
    1. 10.1Layout Guidelines
      1. 10.1.1PCB Layout Guidelines for Internal ASIC Power
      2. 10.1.2PCB Layout Guidelines for Auto-Lock Performance
      3. 10.1.3DMD Interface Considerations
      4. 10.1.4Layout Example
      5. 10.1.5Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Video Timing Parameter Definitions
      2. 11.1.2Device Nomenclature
      3. 11.1.3Device Markings
        1. 11.1.3.1Device Marking
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Features

  • Provides Two 30-bit Input Pixel Interfaces or One 60-bit Input Pixel Interface:
    • YUV, YCrCb, or RGB Data Format
    • 8, 9 or 10 Bits per Color
    • Pixel Clock Support Up to 175 MHz for 30-bit and 160 MHz for 60-bit
  • Supports 24-30 Hz and 47-120 Hz Frame Rates
  • Full Single DLP Controller Support For DMD™s Up to 1920 Pixels Wide
  • Dual DLP Controller Support For Up to 4K Ultra High Definition (UHD) Resolution Display Using DLP660TE TRP DMD
  • High-Speed, Low Voltage Differential Signaling (LVDS) DMD Interface
  • 150 MHz ARM946™ Microprocessor
  • Microprocessor Peripherals
    • Programmable Pulse-Width Modulation (PWM) and Capture Timers
    • Three I2C Ports, Three UART Ports and Three SSP Ports
    • One USB 1.1 Slave Port
  • Image Processing
    • Multiple Image Processing Algorithms
    • Frame Rate Conversion
    • Color Coordinate Adjustment
    • Programmable Color Space Conversion
    • Programmable Degamma and Splash
    • Integrated Support for 3-D Display
  • On-Screen Display (OSD)
  • Integrated Clock Generation Circuitry
    • Operates on a Single 20 MHz Crystal
    • Integrated Spread Spectrum Clocking
  • External Memory Support
    • Parallel Flash for Microprocessor and PWM Sequence
    • Optional SRAM
  • 516 Pin Plastic Ball Grid Array Package
  • Supports Lamp, LED, and Laser Hybrid Illumination Systems

Applications

  • 4K Ultra High Definition (UHD) Display
  • Laser TV
  • Digital Signage
  • Projection Mapping

Description

DLPC4422 is a digital display controller for the DLP 4K UHD display chipset. The DLPC4422 display controller, together with the DLP660TE DMD and DLPA100 power management and motor driver device, comprise the chipset. This solution is a great fit for display systems that require high resolution, high brightness and system simplicity. To ensure reliable operation, the DLPC4422 display controller must always be used with the DLP660TE DMD and the DLPA100 power management and motor driver device.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
DLPC4422ZPC (516)27.00 mm × 27.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

DLPC4422 DLPA100_SBD.jpg