DLPS074 February 2017 DLPC4422
PRODUCTION DATA.
TI recommends 2-ounce copper planes in the PCB design to achieve needed thermal connectivity.
TI recommends the following guidelines to achieve desired ASIC performance relative to internal PLLs:
High frequency decoupling is required for both 1.1-V and 1.8-V PLL supplies and should be provided as close as possible to each of the PLL supply package pins. TI recommends placing decoupling capacitors under the package on the opposite side of the board. Use high quality, low-ESR, monolithic, surface mount capacitors. Typically 0.1µF for each PLL supply should be sufficient. The length of a connecting trace increases the parasitic inductance of the mounting and thus, where possible, there should be no trace, allowing the via to butt up against the land itself. Additionally, the connecting trace should be made as wide as possible. Further improvement can be made by placing vias to the side of the capacitor lands or doubling the number of vias.
The location of bulk decoupling depends on the system design.
One of the most important factors in getting good performance from Auto-Lock is to design the PCB with the highest quality signal integrity possible. TI recommends the following:
High speed interface waveform quality and timing on the DLPC4422 device (i.e. the LVDS DMD Interface) is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus ensuring positive timing margin requires attention to many factors.
As an example, DMD Interface system timing margin can be calculated as follows:
Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously switching output (SSO) noise, cross-talk and inter-symbol interference (ISI) noise. The DLPC4422 device I/O timing parameters as well as DMD I/O timing parameters can be easily found in their corresponding datasheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation is not so straight forward.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements
PDB Design:
● Configuration | Asymmetric Dual Stripline |
● Etch Thickness | 1.0 oz copper (1.2 mil) |
● Flex Etch Thickness | 0.5 oz copper (0.6 mil) |
● Single Ended Signal Impedance | 50 ohms (+/- 10%) |
● Differential Signal Impedance | 100 ohms differential (+/- 10%) |
PCB Stackup:
● Reference plane 1 is assumed to be a ground plane for proper return path | |
● Reference plane 2 is assumed to be the I/O power plane or ground | |
● Dielectric FR4, (Er): | 4.2 (nominal) |
● Signal trace distance to reference plane 1 (H1) | 5.0 mil (nominal) |
● Signal trace distance to reference plane 2 (H2) | 34.2 mil (nominal) |
PARAMETER | APPLICATION | SINGLE-ENDED SIGNAL | DIFFERENTIAL PAIRS | UNIT |
---|---|---|---|---|
Line width (W)(1) | Escape Routing in Ball Field | 4 (0.1) | 4 (0.1) | mil (mm) |
PCB Etch Data or Control | 7 (0.18) | 4.25 (0.11) | mil (mm) | |
PCB Etch Clocks | 7 (0.18) | 4.25 (0.11) | mil (mm) | |
Minimum Line spacing to other signals (S) | Escape Routing in Ball Field | 4 (0.1) | 4 (0.1) | mil (mm) |
PCB Etch Data or Control | 10 (0.25) | 20 (0.51) | mil (mm) | |
PCB Etch Clocks | 20 (0.51) | 20 (0.51) | mil (mm) |
SIGNAL GROUP LENGTH MATCHING | ||||
---|---|---|---|---|
I/F | SIGNAL GROUP | REFERENCE SIGNAL | MAX MISMATCH | UNIT |
DMD (LVDS) | SCA_P,SCA_N, DDA_P(15:0), DDA_N(15:0) | DCKA_P, DCKA_N | +/-150 (+/-3.81) | mil (mm) |
DMD (LVDS) | SCB_P,SCB_N, DDB_P(15:0), DDB_N(15:0) | DCKB_P, DCKB_N | +/-150 (+/-3.81) | mil (mm) |
Number of layer changes:
Termination requirements:
Connector (DMD-LVDS I/F bus only) - High Speed Connectors that meet the following requirements should be used:
● Differential Crosstalk | <5 % |
● Differential Impedance | 75-125 ohms |
Routing requirements for right angle connectors:
When using right angle connectors, P-N pairs should be routed in same row to minimize delay mismatch. When using right angle connectors, propagation delay difference for each row should be accounted for on associated PCB etch lengths.
The underlying thermal limitation for the DLPC4422 device is that the maximum operating junction temperature (TJ) not be exceeded (this is defined Recommended Operating Conditions). This temperature is dependent on operating ambient temperature, airflow, PCB design (including the component layout density and the amount of copper used), power dissipation of the DLPC4422 device and power dissipation of surrounding components. The DLPC4422 package is designed primarily to extract heat through the power and ground planes of the PCB, thus copper content and airflow over the PCB are important factors.
The recommended maximum operating ambient temperature (TA) is provided primarily as a design target and is based on maximum DLPC4422 power dissipation and RθJA at 1 m/s of forced airflow, where RθJA is the thermal resistance of the package as measured using a JEDEC defined standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC4422 PCB, and thus the reported thermal resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different, it is the best information available during the design phase to estimate thermal performance. However, after the PCB is designed and the product is built, TI highly recommends that thermal performance be measured and validated.
To do this, the top center case temperature should be measured under the worse case product scenario (max power dissipation, max voltage, max ambient temp) and validated not to exceed the maximum recommended case temperature (TC). This specification is based on the measured φJT for the DLPC4422 package and provides a relatively accurate correlation to junction temperature. Note that care must be taken when measuring this case temperature to prevent accidental cooling of the package surface. TI recommends a small (approx 40 gauge) thermocouple. The bead and the thermocouple wire should contact the top of the package and be covered with a minimal amount of thermally conductive epoxy. The wires should be routed closely along the package and the board surface to avoid cooling the bead through the wires.