SPRS976D November 2016  – July 2017 DM505

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3 Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Device Comparison Table
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagram
    2. 4.2Pin Attributes
    3. 4.3Signal Descriptions
      1. 4.3.1 VIP
      2. 4.3.2 DSS
      3. 4.3.3 SD_DAC
      4. 4.3.4 ADC
      5. 4.3.5 Camera Control
      6. 4.3.6 CPI
      7. 4.3.7 CSI2
      8. 4.3.8 EMIF
      9. 4.3.9 GPMC
      10. 4.3.10Timers
      11. 4.3.11I2C
      12. 4.3.12UART
      13. 4.3.13McSPI
      14. 4.3.14QSPI
      15. 4.3.15McASP
      16. 4.3.16DCAN and MCAN
      17. 4.3.17GMAC_SW
      18. 4.3.18SDIO Controller
      19. 4.3.19GPIO
      20. 4.3.20ePWM
      21. 4.3.21Emulation and Debug Subsystem
      22. 4.3.22System and Miscellaneous
        1. 4.3.22.1Sysboot
        2. 4.3.22.2Power, Reset and Clock Management (PRCM)
        3. 4.3.22.3Enhanced Direct Memory Access (EDMA)
        4. 4.3.22.4Interrupt Controllers (INTC)
      23. 4.3.23Power Supplies
    4. 4.4Pin Multiplexing
    5. 4.5Connections for Unused Pins
  5. 5Specifications
    1. 5.1Absolute Maximum Ratings
    2. 5.2ESD Ratings
    3. 5.3Power on Hour (POH) Limits
    4. 5.4Recommended Operating Conditions
    5. 5.5Operating Performance Points
      1. 5.5.1AVS Requirements
      2. 5.5.2Voltage And Core Clock Specifications
      3. 5.5.3Maximum Supported Frequency
    6. 5.6Power Consumption Summary
    7. 5.7Electrical Characteristics
    8. 5.8Thermal Characteristics
      1. 5.8.1Package Thermal Characteristics
    9. 5.9Timing Requirements and Switching Characteristics
      1. 5.9.1Timing Parameters and Information
      2. 5.9.2Interface Clock Specifications
        1. 5.9.2.1Interface Clock Terminology
        2. 5.9.2.2Interface Clock Frequency
      3. 5.9.3Power Supply Sequences
      4. 5.9.4Clock Specifications
        1. 5.9.4.1Input Clocks / Oscillators
          1. 5.9.4.1.1OSC0 External Crystal
          2. 5.9.4.1.2OSC0 Input Clock
          3. 5.9.4.1.3Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1OSC1 External Crystal
            2. 5.9.4.1.3.2OSC1 Input Clock
          4. 5.9.4.1.4RC On-die Oscillator Clock
        2. 5.9.4.2Output Clocks
        3. 5.9.4.3DPLLs, DLLs
          1. 5.9.4.3.1DPLL Characteristics
          2. 5.9.4.3.2DLL Characteristics
            1. 5.9.4.3.2.1DPLL and DLL Noise Isolation
      5. 5.9.5Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6Peripherals
        1. 5.9.6.1 Timing Test Conditions
        2. 5.9.6.2 VIP
        3. 5.9.6.3 DSS
        4. 5.9.6.4 ISS
          1. 5.9.6.4.1CSI-2 MIPI D-PHY—1.5 V and 1.8 V
        5. 5.9.6.5 EMIF
        6. 5.9.6.6 GPMC
          1. 5.9.6.6.1GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.6.2GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.6.3GPMC/NAND Flash Interface Asynchronous Timing
        7. 5.9.6.7 GP Timers
          1. 5.9.6.7.1GP Timer Features
        8. 5.9.6.8 I2C
        9. 5.9.6.9 UART
        10. 5.9.6.10McSPI
        11. 5.9.6.11QSPI
        12. 5.9.6.12McASP
        13. 5.9.6.13DCAN and MCAN
          1. 5.9.6.13.1DCAN
          2. 5.9.6.13.2MCAN
        14. 5.9.6.14GMAC_SW
          1. 5.9.6.14.1GMAC MDIO Interface Timings
          2. 5.9.6.14.2GMAC RGMII Timings
        15. 5.9.6.15SDIO Controller
          1. 5.9.6.15.1MMC, SD Default Speed
          2. 5.9.6.15.2MMC, SD High Speed
          3. 5.9.6.15.3MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.15.4MMC, SD SDR25 Mode
        16. 5.9.6.16GPIO
      7. 5.9.7Emulation and Debug Subsystem
        1. 5.9.7.1JTAG Electrical Data/Timing
        2. 5.9.7.2Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2 Functional Block Diagram
    3. 6.3 DSP Subsystem
    4. 6.4 IPU
    5. 6.5 EVE
    6. 6.6 Memory Subsystem
      1. 6.6.1EMIF
      2. 6.6.2GPMC
      3. 6.6.3ELM
      4. 6.6.4OCMC
    7. 6.7 Interprocessor Communication
      1. 6.7.1Mailbox
      2. 6.7.2Spinlock
    8. 6.8 Interrupt Controller
    9. 6.9 EDMA
    10. 6.10Peripherals
      1. 6.10.1 VIP
      2. 6.10.2 DSS
      3. 6.10.3 ADC
      4. 6.10.4 ISS
      5. 6.10.5 Timers
        1. 6.10.5.1General-Purpose Timers
        2. 6.10.5.232-kHz Synchronized Timer (COUNTER_32K)
      6. 6.10.6 I2C
      7. 6.10.7 UART
        1. 6.10.7.1UART Features
      8. 6.10.8 McSPI
      9. 6.10.9 QSPI
      10. 6.10.10McASP
      11. 6.10.11DCAN
      12. 6.10.12MCAN
      13. 6.10.13GMAC_SW
      14. 6.10.14SDIO
      15. 6.10.15GPIO
      16. 6.10.16ePWM
      17. 6.10.17eCAP
      18. 6.10.18eQEP
    11. 6.11On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1Step 1: PCB Stack-up
      2. 7.2.2Step 2: Physical Placement
      3. 7.2.3Step 3: Static Analysis
        1. 7.2.3.1PDN Resistance and IR Drop
      4. 7.2.4Step 4: Frequency Analysis
      5. 7.2.5System ESD Generic Guidelines
        1. 7.2.5.1System ESD Generic PCB Guideline
        2. 7.2.5.2Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3ESD Protection System Design Consideration
      6. 7.2.6EMI / EMC Issues Prevention
        1. 7.2.6.1Signal Bandwidth
        2. 7.2.6.2Signal Routing
          1. 7.2.6.2.1Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2Signal Routing—Outer Layer Routing
        3. 7.2.6.3Ground Guidelines
          1. 7.2.6.3.1PCB Outer Layers
          2. 7.2.6.3.2Metallic Frames
          3. 7.2.6.3.3Connectors
          4. 7.2.6.3.4Guard Ring on PCB Edges
          5. 7.2.6.3.5Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1General Constraints and Theory
      2. 7.3.2Voltage Decoupling
      3. 7.3.3Static PDN Analysis
      4. 7.3.4Dynamic PDN Analysis
      5. 7.3.5Power Supply Mapping
      6. 7.3.6DPLL Voltage Requirement
      7. 7.3.7Example PCB Design
        1. 7.3.7.1Example Stack-up
        2. 7.3.7.2vdd_dspeve Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1General Routing Guidelines
      2. 7.4.2QSPI Board Design and Layout Guidelines
        1. 7.4.2.1If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5 Differential Interfaces
      1. 7.5.1General Routing Guidelines
      2. 7.5.2CSI2 Board Design and Routing Guidelines
        1. 7.5.2.1CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.2.1.1General Guidelines
          2. 7.5.2.1.2Length Mismatch Guidelines
            1. 7.5.2.1.2.1CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.2.1.3Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1Oscillator Ground Connection
    7. 7.7 LPDDR2 Board Design and Layout Guidelines
      1. 7.7.1LPDDR2 Board Designs
      2. 7.7.2LPDDR2 Device Configurations
      3. 7.7.3LPDDR2 Interface
        1. 7.7.3.1LPDDR2 Interface Schematic
        2. 7.7.3.2Compatible JEDEC LPDDR2 Devices
        3. 7.7.3.3LPDDR2 PCB Stackup
        4. 7.7.3.4LPDDR2 Placement
        5. 7.7.3.5LPDDR2 Keepout Region
        6. 7.7.3.6LPDDR2 Net Classes
        7. 7.7.3.7LPDDR2 Signal Termination
        8. 7.7.3.8LPDDR2 DDR_VREF Routing
      4. 7.7.4Routing Specification
        1. 7.7.4.1DQS[x] and DQ[x] Routing Specification
        2. 7.7.4.2CK and ADDR_CTRL Routing Specification
    8. 7.8 DDR2 Board Design and Layout Guidelines
      1. 7.8.1DDR2 General Board Layout Guidelines
      2. 7.8.2DDR2 Board Design and Layout Guidelines
        1. 7.8.2.1Board Designs
        2. 7.8.2.2DDR2 Interface
          1. 7.8.2.2.1 DDR2 Interface Schematic
          2. 7.8.2.2.2 Compatible JEDEC DDR2 Devices
          3. 7.8.2.2.3 PCB Stackup
          4. 7.8.2.2.4 Placement
          5. 7.8.2.2.5 DDR2 Keepout Region
          6. 7.8.2.2.6 Bulk Bypass Capacitors
          7. 7.8.2.2.7 High-Speed Bypass Capacitors
          8. 7.8.2.2.8 Net Classes
          9. 7.8.2.2.9 DDR2 Signal Termination
          10. 7.8.2.2.10VREF Routing
        3. 7.8.2.3DDR2 CK and ADDR_CTRL Routing
    9. 7.9 DDR3 Board Design and Layout Guidelines
      1. 7.9.1DDR3 General Board Layout Guidelines
      2. 7.9.2DDR3 Board Design and Layout Guidelines
        1. 7.9.2.1 Board Designs
        2. 7.9.2.2 DDR3 Device Combinations
        3. 7.9.2.3 DDR3 Interface Schematic
          1. 7.9.2.3.132-Bit DDR3 Interface
          2. 7.9.2.3.216-Bit DDR3 Interface
        4. 7.9.2.4 Compatible JEDEC DDR3 Devices
        5. 7.9.2.5 PCB Stackup
        6. 7.9.2.6 Placement
        7. 7.9.2.7 DDR3 Keepout Region
        8. 7.9.2.8 Bulk Bypass Capacitors
        9. 7.9.2.9 High-Speed Bypass Capacitors
          1. 7.9.2.9.1Return Current Bypass Capacitors
        10. 7.9.2.10Net Classes
        11. 7.9.2.11DDR3 Signal Termination
        12. 7.9.2.12VTT
        13. 7.9.2.13CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.9.2.13.1Three DDR3 Devices
            1. 7.9.2.13.1.1CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.9.2.13.1.2CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.9.2.13.2Two DDR3 Devices
            1. 7.9.2.13.2.1CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.9.2.13.2.2CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.9.2.13.3One DDR3 Device
            1. 7.9.2.13.3.1CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.9.2.13.3.2CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.9.2.14Data Topologies and Routing Definition
          1. 7.9.2.14.1DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.9.2.14.2DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.9.2.15Routing Specification
          1. 7.9.2.15.1CK and ADDR_CTRL Routing Specification
          2. 7.9.2.15.2DQS and DQ Routing Specification
    10. 7.10CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1Device Nomenclature
      1. 8.1.1Standard Package Symbolization
      2. 8.1.2Device Naming Convention
    2. 8.2Tools and Software
    3. 8.3Documentation Support
      1. 8.3.1FCC Warning
      2. 8.3.2Information About Cautions and Warnings
    4. 8.4Receiving Notification of Documentation Updates
    5. 8.5Community Resources
    6. 8.6Trademarks
      1. 8.6.1Electrostatic Discharge Caution
    7. 8.7Export Control Notice
    8. 8.8Glossary
  9. 9Mechanical Packaging Information
    1. 9.1Mechanical Data

Device Overview

Features

  • Architecture Designed for Vision Analytics Applications
  • Video and Image Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Video Input and Video Output
  • Up to 2 C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible With C67x and C64x+
    • Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 512kB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Memory Interface (EMIF) Module
    • Supports DDR3/DDR3L up to DDR-1066
    • Supports DDR2 up to DDR-800
    • Supports LPDDR2 up to DDR-667
    • Up to 2GB Supported
  • Dual ARM® Cortex®-M4 Image Processor (IPU)
  • Vision AccelerationPac
    • Embedded Vision Engine (EVE)
  • Display Subsystem
    • Display Controller With DMA Engine
    • CVIDEO / SD-DAC TV Analog Composite Output
  • Video Input Port (VIP) Module
    • Support for up to 4 Multiplexed Input Ports
  • On-chip Temperature Sensor That is Capable of Generating Temperature Alerts
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 3-Port (2 External) Gigabit Ethernet (GMAC) Switch
  • Controller Area Network (DCAN) Module
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol
  • Eight 32-Bit General-Purpose Timers
  • Three Configurable UART Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface
  • Two Inter-Integrated Circuit (I2C) Ports
  • Three Multichannel Audio Serial Ports (McASP) Modules
  • MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO)
  • Up to 126 General-Purpose I/O (GPIO) Pins
  • Power, Reset, and Clock Management
  • On-Chip Debug With CTools Technology
  • Automotive AEC-Q100 Qualified
  • 15 × 15mm, 0.65-mm Pitch, 367-Pin PBGA (ABF)
  • 8-Channel 10-bit ADC
  • MIPI CSI-2 Camera Serial Interface
  • PWMSS
  • Full HW Image Pipe: DPC, CFA, 3D-NF, RGB-YUV
    • WDR, HW LDC and Perspective

Applications

  • Drones
  • Robotics
  • Industrial Transportation (Forklift, Rail, Agriculture)
  • Factory and Building Automation cameras

Description

The DM505 is a highly optimized device for Vision Analytics and Machine Vision processing in Industrial products such as drones, robots, forklifts, railroad and agriculture equipment. The Processor enables sophisticated embedded vision processing integrating an optimal mix of real time performance, low power, small form factor and camera processing for systems to interact in more intelligent, useful ways with the physical world and the people in it.

The DM505 incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac (EVE), and dual-Cortex-M4 processors. The device allows low power designs to meet demanding embedded system budgets without sacrificing real-time processing performance to enable small form factor designs. The DM505 also integrates a host of peripherals including interfaces for multi-camera input (both parallel and serial), display outputs, audio and serial I/O, CAN and GigB Ethernet AVB.

TI provides application specific hardware and software through our Design Network Partners and a complete set of development tools for the ARM, and DSP, including C compilers with TI RTOS to accelerate time to market.

Device Information

PART NUMBERPACKAGEBODY SIZE
DM505S-PBGA (367)15.0 mm × 15.0 mm

Functional Block Diagram

Figure 1-1 is functional block diagram of the superset.

DM505 SPRS916_Intro_001_SR2.gif Figure 1-1 DM505 Block Diagram