SLLSEJ7 February 2015 DP83848-HT

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Typical System Diagram
  5. Revision History
  6. Bare Die Information
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5DC Electrical Characteristics
    6. 7.6AC Timing Specifications
    7. 7.7Typical Characteristics
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1100BASE-TX Transmitter
        1. 8.3.1.1Code-Group Encoding and Injection
        2. 8.3.1.2Scrambler
        3. 8.3.1.3NRZ to NRZI Encoder
        4. 8.3.1.4Binary to MLT-3 Convertor
      2. 8.3.2100BASE-TX Receiver
        1. 8.3.2.1 Analog Front End
        2. 8.3.2.2 Digital Signal Processor
          1. 8.3.2.2.1Digital Adaptive Equalization and Gain Control
          2. 8.3.2.2.2Base Line Wander Compensation
        3. 8.3.2.3 Signal Detect
        4. 8.3.2.4 MLT-3 to NRZI Decoder
        5. 8.3.2.5 NRZI to NRZ
        6. 8.3.2.6 Serial to Parallel
        7. 8.3.2.7 Descrambler
        8. 8.3.2.8 Code-Group Alignment
        9. 8.3.2.9 4B/5B Decoder
        10. 8.3.2.10100BASE-TX Link Integrity Monitor
        11. 8.3.2.11Bad SSD Detection
      3. 8.3.310BASE-T Transceiver Module
        1. 8.3.3.1 Operational Modes
          1. 8.3.3.1.1Half Duplex Mode
          2. 8.3.3.1.2Full Duplex Mode
        2. 8.3.3.2 Smart Squelch
        3. 8.3.3.3 Collision Detection and SQE
        4. 8.3.3.4 Carrier Sense
        5. 8.3.3.5 Normal Link Pulse Detection/Generation
        6. 8.3.3.6 Jabber Function
        7. 8.3.3.7 Automatic Link Polarity Detection and Correction
        8. 8.3.3.8 Transmit and Receive Filtering
        9. 8.3.3.9 Transmitter
        10. 8.3.3.10Receiver
      4. 8.3.4Reset Operation
        1. 8.3.4.1Hardware Reset
        2. 8.3.4.2Software Reset
    4. 8.4Device Functional Modes
      1. 8.4.1MII Interface
        1. 8.4.1.1Nibble-Wide MII Data Interface
        2. 8.4.1.2Collision Detect
        3. 8.4.1.3Carrier Sense
      2. 8.4.2Reduced MII Interface
      3. 8.4.310 Mb Serial Network Interface (SNI)
      4. 8.4.4802.3u MII Serial Management Interface
        1. 8.4.4.1Serial Management Register Access
        2. 8.4.4.2Serial Management Access Protocol
        3. 8.4.4.3Serial Management Preamble Suppression
    5. 8.5Programming
      1. 8.5.1Auto-Negotiation
        1. 8.5.1.1Auto-Negotiation Pin Control
        2. 8.5.1.2Auto-Negotiation Register Control
        3. 8.5.1.3Auto-Negotiation Parallel Detection
        4. 8.5.1.4Auto-Negotiation Restart
        5. 8.5.1.5Enabling Auto-Negotiation via Software
        6. 8.5.1.6Auto-Negotiation Complete Time
      2. 8.5.2Auto-MDIX
      3. 8.5.3PHY Address
        1. 8.5.3.1MII Isolate Mode
      4. 8.5.4LED Interface
        1. 8.5.4.1LEDs
        2. 8.5.4.2LED Direct Control
      5. 8.5.5Half Duplex vs Full Duplex
      6. 8.5.6Internal Loopback
      7. 8.5.7BIST
    6. 8.6Register Maps
      1. 8.6.1Register Block
      2. 8.6.2Register Definition
        1. 8.6.2.1Basic Mode Control Register (BMCR)
        2. 8.6.2.2Basic Mode Status Register (BMSR)
        3. 8.6.2.3PHY Identifier Register 1 (PHYIDR1)
        4. 8.6.2.4PHY Identifier Register 2 (PHYIDR2)
        5. 8.6.2.5Auto-Negotiation Advertisement Register (ANAR)
        6. 8.6.2.6Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 8.6.2.7Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 8.6.2.8Auto-Negotiate Expansion Register (ANER)
        9. 8.6.2.9Auto-Negotiation Next Page Transmit Register (ANNPTR)
      3. 8.6.3Extended Registers
        1. 8.6.3.1 PHY Status Register (PHYSTS)
        2. 8.6.3.2 MII Interrupt Control Register (MICR)
        3. 8.6.3.3 MII Interrupt Status and Miscellaneous Control Register (MISR)
        4. 8.6.3.4 False Carrier Sense Counter Register (FCSCR)
        5. 8.6.3.5 Receiver Error Counter Register (RECR)
        6. 8.6.3.6 100 Mb/s PCS Configuration and Status Register (PCSR)
        7. 8.6.3.7 RMII and Bypass Register (RBR)
        8. 8.6.3.8 LED Direct Control Register (LEDCR)
        9. 8.6.3.9 PHY Control Register (PHYCR)
        10. 8.6.3.1010Base-T Status/Control Register (10BTSCR)
        11. 8.6.3.11CD Test and BIST Extensions Register (CDCTRL1)
        12. 8.6.3.12Energy Detect Control (EDCR)
  9. Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
        1. 9.2.1.1Clock Requirements
        2. 9.2.1.2Magnetics
      2. 9.2.2Detailed Design Procedure
        1. 9.2.2.1TPI Network Circuit
        2. 9.2.2.2Clock In (X1) Requirements
          1. 9.2.2.2.1Oscillator
          2. 9.2.2.2.2Crystal
        3. 9.2.2.3Power Feedback Circuit
        4. 9.2.2.4Power Down and Interrupt
          1. 9.2.2.4.1Power-Down Control Mode
          2. 9.2.2.4.2Interrupt Mechanisms
        5. 9.2.2.5Energy Detect Mode
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1PCB Layer Stacking
    2. 11.2Layout Example
    3. 11.3ESD Protection
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Trademarks
    3. 12.3Electrostatic Discharge Caution
    4. 12.4Glossary
  13. 13Mechanical, Packaging, and Orderable Information

1 Features

  • Low-Power 3.3-V, 0.18-μm CMOS Technology
  • Low Power Consumption <270 mW Typical
  • 3.3-V MAC Interface
  • Auto-MDIX for 10/100 Mb/s
  • Energy Detection Mode
  • 25-MHz Clock Out
  • SNI Interface (Configurable)
  • RMII Rev. 1.2 Interface (Configurable)
  • MII Serial Management Interface (MDC and MDIO)
  • IEEE 802.3u MII
  • IEEE 802.3u Auto-Negotiation and Parallel Detection
  • IEEE 802.3u ENDEC, 10BASE-T Transceivers and Filters
  • IEEE 802.3u PCS, 100BASE-TX Transceivers and Filters
  • IEEE 1149.1 JTAG
  • Integrated ANSI X3.263 Compliant TP-PMD Physical Sublayer With Adaptive Equalization and Baseline Wander Compensation
  • Error-Free Operation up to 150 Meters
  • Programmable LED Support Link, 10 /100 Mb/s Mode, Activity, and Collision Detect
  • Single Register Access for Complete PHY Status
  • 10/100 Mb/s Packet BIST (Built-in Self Test)
  • Supports Defense, Aerospace, and Medical Applications
    • Controlled Baseline
    • One Assembly and Test Site
    • One Fabrication Site
    • Extended Temperature Range (–55°C to 150°C)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

2 Applications

  • Automotive and Transportation
  • Industrial Controls and Factory Automation
  • General Embedded Applications

3 Description

The number of applications requiring ethernet connectivity continues to increase. Along with this increased market demand is a change in application requirements. The DP83848 was designed to allow ethernet connectivity in the harshest environments. This device is ideally suited for harsh environments for example wireless remote base stations, automotive, transportation and industrial control applications.

The DP83848 is a highly-reliable, feature-rich robust device which includes enhanced ESD protection, MII and RMII for maximum flexibility in MPU selection.

The DP83848 features integrated sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols, which ensures compatibility and interoperability with all other standards based Ethernet solutions.

Device Information(1)

PART NUMBERDIEDIE SIZE (NOM)
DP83848-HTKGD (49)1592 µm × 1532 µm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Typical System Diagram

typical_application.gif