SPRS956D March 2016  – September 2017 DRA722 , DRA724 , DRA725 , DRA726

PRODUCTION DATA. 

  1. Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3 Description
    4. 1.4Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1Device Comparison Table
  4. Terminal Configuration and Functions
    1. 4.1Terminal Assignment
      1. 4.1.1Unused Balls Connection Requirements
    2. 4.2Ball Characteristics
    3. 4.3Multiplexing Characteristics
    4. 4.4Signal Descriptions
      1. 4.4.1 Video Input Ports (VIP)
      2. 4.4.2 Display Subsystem - Video Output Ports
      3. 4.4.3 Display Subsystem - High-Definition Multimedia Interface (HDMI)
      4. 4.4.4 Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5 External Memory Interface (EMIF)
      6. 4.4.6 General-Purpose Memory Controller (GPMC)
      7. 4.4.7 Timers
      8. 4.4.8 Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9 HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13Multicannel Audio Serial Port (McASP)
      14. 4.4.14Universal Serial Bus (USB)
      15. 4.4.15SATA
      16. 4.4.16Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17Controller Area Network Interface (DCAN)
      18. 4.4.18Ethernet Interface (GMAC_SW)
      19. 4.4.19Media Local Bus (MLB) Interface
      20. 4.4.20eMMC/SD/SDIO
      21. 4.4.21General-Purpose Interface (GPIO)
      22. 4.4.22Keyboard controller (KBD)
      23. 4.4.23Pulse Width Modulation (PWM) Interface
      24. 4.4.24Audio Tracking Logic (ATL)
      25. 4.4.25Test Interfaces
      26. 4.4.26System and Miscellaneous
        1. 4.4.26.1Sysboot
        2. 4.4.26.2Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3Real-Time Clock (RTC) Interface
        4. 4.4.26.4System Direct Memory Access (SDMA)
        5. 4.4.26.5Interrupt Controllers (INTC)
        6. 4.4.26.6Observability
      27. 4.4.27Power Supplies
  5. Specifications
    1. 5.1Absolute Maximum Ratings
    2. 5.2ESD Ratings
    3. 5.3Power on Hour (POH) Limits
    4. 5.4Recommended Operating Conditions
    5. 5.5Operating Performance Points
      1. 5.5.1AVS and ABB Requirements
      2. 5.5.2Voltage And Core Clock Specifications
      3. 5.5.3Maximum Supported Frequency
    6. 5.6Power Consumption Summary
    7. 5.7Electrical Characteristics
      1. 5.7.1 LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2 HDMIPHY DC Electrical Characteristics
      3. 5.7.3 Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4 IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5 IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6 LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8 BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9 BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10USBPHY DC Electrical Characteristics
      11. 5.7.11Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13SATAPHY DC Electrical Characteristics
      14. 5.7.14PCIEPHY DC Electrical Characteristics
    8. 5.8Thermal Characteristics
      1. 5.8.1Package Thermal Characteristics
    9. 5.9Power Supply Sequences
  6. Clock Specifications
    1. 6.1Input Clock Specifications
      1. 6.1.1Input Clock Requirements
      2. 6.1.2System Oscillator OSC0 Input Clock
        1. 6.1.2.1OSC0 External Crystal
        2. 6.1.2.2OSC0 Input Clock
      3. 6.1.3Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1OSC1 External Crystal
        2. 6.1.3.2OSC1 Input Clock
      4. 6.1.4RTC Oscillator Input Clock
        1. 6.1.4.1RTC Oscillator External Crystal
        2. 6.1.4.2RTC Oscillator Input Clock
        3. 6.1.4.3RC On-die Oscillator Clock
    2. 6.2DPLLs, DLLs Specifications
      1. 6.2.1DPLL Characteristics
      2. 6.2.2DLL Characteristics
      3. 6.2.3DPLL and DLL Noise Isolation
  7. Timing Requirements and Switching Characteristics
    1. 7.1 Timing Test Conditions
    2. 7.2 Interface Clock Specifications
      1. 7.2.1Interface Clock Terminology
      2. 7.2.2Interface Clock Frequency
    3. 7.3 Timing Parameters and Information
      1. 7.3.1Parameter Information
        1. 7.3.1.11.8V and 3.3V Signal Transition Levels
        2. 7.3.1.21.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3Timing Parameters and Board Routing Analysis
    4. 7.4 Recommended Clock and Control Signal Transition Behavior
    5. 7.5 Virtual and Manual I/O Timing Modes
    6. 7.6 Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8 Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9 Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1CSI-2 MIPI D-PHY
    10. 7.10External Memory Interface (EMIF)
    11. 7.11General-Purpose Memory Controller (GPMC)
      1. 7.11.1GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12Timers
    13. 7.13Inter-Integrated Circuit Interface (I2C)
    14. 7.14HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1HDQ / 1-Wire - HDQ Mode
      2. 7.14.2HDQ/1-Wire-1-Wire Mode
    15. 7.15Universal Asynchronous Receiver Transmitter (UART)
    16. 7.16Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17Quad Serial Peripheral Interface (QSPI)
    18. 7.18Multichannel Audio Serial Port (McASP)
    19. 7.19Universal Serial Bus (USB)
      1. 7.19.1USB1 DRD PHY
      2. 7.19.2USB2 PHY
      3. 7.19.3USB3 DRD ULPI-SDR-Slave Mode-12-pin Mode
    20. 7.20Serial Advanced Technology Attachment (SATA)
    21. 7.21Peripheral Component Interconnect Express (PCIe)
    22. 7.22Controller Area Network Interface (DCAN)
    23. 7.23Ethernet Interface (GMAC_SW)
      1. 7.23.1GMAC MII Timings
      2. 7.23.2GMAC MDIO Interface Timings
      3. 7.23.3GMAC RMII Timings
      4. 7.23.4GMAC RGMII Timings
    24. 7.24Media Local Bus (MLB) interface
    25. 7.25eMMC/SD/SDIO
      1. 7.25.1MMC1-SD Card Interface
        1. 7.25.1.1Default speed, 4-bit data, SDR, half-cycle
        2. 7.25.1.2High speed, 4-bit data, SDR, half-cycle
        3. 7.25.1.3SDR12, 4-bit data, half-cycle
        4. 7.25.1.4SDR25, 4-bit data, half-cycle
        5. 7.25.1.5UHS-I SDR50, 4-bit data, half-cycle
        6. 7.25.1.6UHS-I SDR104, 4-bit data, half-cycle
        7. 7.25.1.7UHS-I DDR50, 4-bit data
      2. 7.25.2MMC2 - eMMC
        1. 7.25.2.1Standard JC64 SDR, 8-bit data, half cycle
        2. 7.25.2.2High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.25.2.3High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
        4. 7.25.2.4High-speed JC64 DDR, 8-bit data
      3. 7.25.3MMC3 and MMC4-SDIO/SD
        1. 7.25.3.1MMC3 and MMC4, SD Default Speed
        2. 7.25.3.2MMC3 and MMC4, SD High Speed
        3. 7.25.3.3MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.25.3.4MMC3 and MMC4, SD SDR25 Mode
        5. 7.25.3.5MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    26. 7.26General-Purpose Interface (GPIO)
    27. 7.27Audio Tracking Logic (ATL)
      1. 7.27.1ATL Electrical Data/Timing
    28. 7.28System and Miscellaneous interfaces
    29. 7.29Test Interfaces
      1. 7.29.1IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.29.1.1JTAG Electrical Data/Timing
      2. 7.29.2Trace Port Interface Unit (TPIU)
        1. 7.29.2.1TPIU PLL DDR Mode
  8. Applications, Implementation, and Layout
    1. 8.1Introduction
      1. 8.1.1Initial Requirements and Guidelines
    2. 8.2Power Optimizations
      1. 8.2.1Step 1: PCB Stack-up
      2. 8.2.2Step 2: Physical Placement
      3. 8.2.3Step 3: Static Analysis
        1. 8.2.3.1PDN Resistance and IR Drop
      4. 8.2.4Step 4: Frequency Analysis
      5. 8.2.5System ESD Generic Guidelines
        1. 8.2.5.1System ESD Generic PCB Guideline
        2. 8.2.5.2Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 8.2.5.3ESD Protection System Design Consideration
      6. 8.2.6EMI / EMC Issues Prevention
        1. 8.2.6.1Signal Bandwidth
        2. 8.2.6.2Signal Routing
          1. 8.2.6.2.1Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2Signal Routing—Outer Layer Routing
        3. 8.2.6.3Ground Guidelines
          1. 8.2.6.3.1PCB Outer Layers
          2. 8.2.6.3.2Metallic Frames
          3. 8.2.6.3.3Connectors
          4. 8.2.6.3.4Guard Ring on PCB Edges
          5. 8.2.6.3.5Analog and Digital Ground
    3. 8.3Core Power Domains
      1. 8.3.1General Constraints and Theory
      2. 8.3.2Voltage Decoupling
      3. 8.3.3Static PDN Analysis
      4. 8.3.4Dynamic PDN Analysis
      5. 8.3.5Power Supply Mapping
      6. 8.3.6DPLL Voltage Requirement
      7. 8.3.7Example PCB Design
        1. 8.3.7.1Example Stack-up
        2. 8.3.7.2vdd Example Analysis
    4. 8.4Single-Ended Interfaces
      1. 8.4.1General Routing Guidelines
      2. 8.4.2QSPI Board Design and Layout Guidelines
    5. 8.5Differential Interfaces
      1. 8.5.1General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1Background
        2. 8.5.2.2USB PHY Layout Guide
          1. 8.5.2.2.1General Routing and Placement
          2. 8.5.2.2.2Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1 Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2 Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3 Board Stackup
            4. 8.5.2.2.2.4 Cable Connector Socket
            5. 8.5.2.2.2.5 Clock Routings
            6. 8.5.2.2.2.6 Crystals/Oscillator
            7. 8.5.2.2.2.7 DP/DM Trace
            8. 8.5.2.2.2.8 DP/DM Vias
            9. 8.5.2.2.2.9 Image Planes
            10. 8.5.2.2.2.10Power Regulators
        3. 8.5.2.3References
      3. 8.5.3USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1USB 3.0 interface introduction
        2. 8.5.3.2USB 3.0 General routing rules
      4. 8.5.4HDMI Board Design and Layout Guidelines
        1. 8.5.4.1HDMI Interface Schematic
        2. 8.5.4.2TMDS General Routing Guidelines
        3. 8.5.4.3TPD5S115
        4. 8.5.4.4HDMI ESD Protection Device (Required)
        5. 8.5.4.5PCB Stackup Specifications
        6. 8.5.4.6Grounding
      5. 8.5.5SATA Board Design and Layout Guidelines
        1. 8.5.5.1SATA Interface Schematic
        2. 8.5.5.2Compatible SATA Components and Modes
        3. 8.5.5.3PCB Stackup Specifications
        4. 8.5.5.4Routing Specifications
      6. 8.5.6PCIe Board Design and Layout Guidelines
        1. 8.5.6.1PCIe Connections and Interface Compliance
          1. 8.5.6.1.1Coupling Capacitors
          2. 8.5.6.1.2Polarity Inversion
        2. 8.5.6.2Non-standard PCIe connections
          1. 8.5.6.2.1PCB Stackup Specifications
          2. 8.5.6.2.2Routing Specifications
            1. 8.5.6.2.2.1Impedance
            2. 8.5.6.2.2.2Differential Coupling
            3. 8.5.6.2.2.3Pair Length Matching
        3. 8.5.6.3LJCB_REFN/P Connections
      7. 8.5.7CSI2 Board Design and Routing Guidelines
        1. 8.5.7.1CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
          1. 8.5.7.1.1General Guidelines
          2. 8.5.7.1.2Length Mismatch Guidelines
            1. 8.5.7.1.2.1CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
          3. 8.5.7.1.3Frequency-domain Specification Guidelines
    6. 8.6Clock Routing Guidelines
      1. 8.6.132-kHz Oscillator Routing
      2. 8.6.2Oscillator Ground Connection
    7. 8.7DDR3 Board Design and Layout Guidelines
      1. 8.7.1DDR3 General Board Layout Guidelines
      2. 8.7.2DDR3 Board Design and Layout Guidelines
        1. 8.7.2.1 Board Designs
        2. 8.7.2.2 DDR3 EMIF
        3. 8.7.2.3 DDR3 Device Combinations
        4. 8.7.2.4 DDR3 Interface Schematic
          1. 8.7.2.4.132-Bit DDR3 Interface
          2. 8.7.2.4.216-Bit DDR3 Interface
        5. 8.7.2.5 Compatible JEDEC DDR3 Devices
        6. 8.7.2.6 PCB Stackup
        7. 8.7.2.7 Placement
        8. 8.7.2.8 DDR3 Keepout Region
        9. 8.7.2.9 Bulk Bypass Capacitors
        10. 8.7.2.10High-Speed Bypass Capacitors
          1. 8.7.2.10.1Return Current Bypass Capacitors
        11. 8.7.2.11Net Classes
        12. 8.7.2.12DDR3 Signal Termination
        13. 8.7.2.13VREF_DDR Routing
        14. 8.7.2.14VTT
        15. 8.7.2.15CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.2.15.1Four DDR3 Devices
            1. 8.7.2.15.1.1CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.2.15.1.2CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.2.15.2Two DDR3 Devices
            1. 8.7.2.15.2.1CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.2.15.2.2CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.2.15.3One DDR3 Device
            1. 8.7.2.15.3.1CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.2.15.3.2CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.2.16Data Topologies and Routing Definition
          1. 8.7.2.16.1DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.2.16.2DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.2.17Routing Specification
          1. 8.7.2.17.1CK and ADDR_CTRL Routing Specification
          2. 8.7.2.17.2DQS and DQ Routing Specification
  9. Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1Standard Package Symbolization
      2. 9.1.2Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Community Resources
    6. 9.6 Related Links
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Export Control Notice
    10. 9.10Glossary
  10. 10Mechanical Packaging and Orderable Information

Device Overview

Features

  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • ARM® Cortex®-A15 Microprocessor Subsystem
  • C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible With C67x and C64x+
    • Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 512KB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • DDR3/DDR3L Memory Interface (EMIF) Module
    • Supports up to DDR3-1333 (667 MHz)
    • Up to 2GB Across Single Chip Select
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD Subsystem
  • Display Subsystem
    • Display Controller With DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante™ GC320 Core
  • Video Processing Engine (VPE)
  • Single-Core PowerVR® SGX544 3D GPU
  • One Video Input Port (VIP) Module
    • Support for up to Four Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
    • Up to Two External Ports
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Six High-Speed Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Real-Time Clock Subsystem (RTCSS)
  • SATA Interface
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • High-Speed USB 2.0 Dual-Role Device
  • High-Speed USB 2.0 On-The-Go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC/SD/SDIO)
  • PCI Express® 3.0 Subsystems With Two 5-Gbps Lanes
    • One 2-lane Gen2-Compliant Port
    • or Two 1-lane Gen2-Compliant Ports
  • Dual Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • MIPI® CSI-2 Camera Serial Interface
  • Up to 215 General-Purpose I/O (GPIO) Pins
  • Power, Reset, and Clock Management
  • On-Chip Debug With CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)

Applications

  • Human-Machine Interface (HMI)
  • Navigation
  • Digital and Analog Radio
  • Rear Seat Entertainment
  • Multimedia Playback
  • AM/FM/RDS and Digital Radio Decoding
  • ADAS and Jacinto 6 Integration

Description

DRA72x ("Jacinto 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution.

Programmability is provided by a single-core ARM Cortex-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The ARM processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the ARM, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.

Device Information

PART NUMBERPACKAGEBODY SIZE
DRA72xFCBGA (760)23.0 mm × 23.0 mm

Functional Block Diagram

Figure 1-1 is functional block diagram for the device.

DRA722 DRA724 DRA725 DRA726 func_sprs906-001.gif Figure 1-1 DRA72x Block Diagram