DRA72x ("Jacinto 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences.
DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution.
Programmability is provided by a single-core ARM Cortex-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The ARM processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the ARM, and DSP, including C compilers and a debugging interface for visibility into source code execution.
The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.
|PART NUMBER||PACKAGE||BODY SIZE|
|DRA72x||FCBGA (760)||23.0 mm × 23.0 mm|
Figure 1-1 is functional block diagram for the device.