DRA80M Up to quad ARM Cortex-A53 and integrated MCU with dual ARM Cortex-R5F for automotive gateway | TI.com

DRA80M
This product is prototype/experimental and has not been released to the market. Testing and final processes may not be complete. This product may be subject to further changes or possible discontinuation.
Up to quad ARM Cortex-A53 and integrated MCU with dual ARM Cortex-R5F for automotive gateway

 

Sample Availability

ACD package is in preview. Preproduction samples are available (X6580ACD). Request now

Description

Automobiles are becoming more and more connected - both inside the car, within the various subsystems/domains as well as with the outside world, with connectivity via Bluetooth, LTE, WiFi etc.

Much more information and data are being shared or transferred between the various domains; for example, video from rear and surround view cameras for displayed in the head unit; data from the chassis is sent to the on-board diagnostic unit, etc. As the amount of data that has to be integrated and transported between the various domains in a time sensitive manner has increased, car manufacturers are looking to include a network gateway, based on Ethernet protocols, in cars. Such gateways should be able to handle multiple connectivity protocols such as CAN, CAN-FD, TCP/IP to name a few. TI’s DRA80x family of products enable automotive manufacturers to build scalable and cost optimized network gateway features in cars, thanks to its high level of integration and purpose built peripherals, such as Gigabit Ethernet MACs.

DRA80x Automotive Gateway processors are built to meet the intense processing needs of automotive gateway. The DRA80x family of devices combines four or two Arm® Cortex®-A53 cores with an ASIL-C capable dual Arm® Cortex®-R5 MCU subsystem and six Gigabit Ethernet MACs in the MAIN domain and one Gigabit Ethernet MAC in the MCU domain to create an SoC capable of implementing an Automotive Gateway system with plenty of automotive connectivity and functional safety processing.

The four Courtex-A53 cores in the DRA804M are arranged in two dual-core clusters with shared L2 memory to create two processing channels to address additional safety concepts. The two Arm® Cortex®-A53 cores in the DRA802M are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included for on-chip memory and interconnects for reliability. Cryptographic acceleration and secure boot are available on some DRA80x devices, in addition to granular whitelist firewalls managed by a security controller core.

Programmability is provided by the Arm® Cortex®-A53 RISC CPUs with Arm® Neon™ extension, and the dual Arm® Cortex®-R5 MCU subsystem is available for general purpose use. The Ethernet subsystem can be used to provide up to six ports of Ethernets, including TSN and Ethernet/IP, for standard Ethernet connectivity. Additionally, TI provides a complete set of development tools for the Arm® cores including C compilers and a debugging interface for visibility into source code execution. Safety documentation is available for applications needing to meet functional safety standards.

Features

  • Processor cores:
  • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm® Cortex®-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core
  • Ethernet subsystem:
  • Three industrial subsystem with Ethernet support:
    • Up to two 10/100/1000 Ethernet ports per subsystem
    • Supports two 10/100/1000 SGMII ports (1)
    • Compatibility with 10/100Mb
  • Memory subsystem:
  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR3L/DDR4 memory types up to DDR-1600
    • Supports LPDDR4 memory type up to DDR-1333
    • 32-bit data bus and 7-bit SECDED bus
    • 32GB of total addressable space
  • General-Purpose Memory Controller (GPMC)
  • SafeTI™ semiconductor component:
  • Designed for functional safety applications
  • Developed according to the requirements of ISO 26262
  • Achieves systematic integrity of ASIL-D
  • For the MCU safety island, sufficient diagnostics are included to achieve random fault integrity requirements of ASIL-B
  • For the rest of the SoC, sufficient diagnostics are included to achieve random fault integrity requirements of ASIL-B
  • In addition, sufficient architectural support is in place to achieve execution of ASIL-D applications given a proper safety concept (for example reciprocal comparison by software)
  • Functional safety manual available
  • Safety-related certification
    • Component level functional safety certification by TÜV SÜD [certification in progress]
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm® Cortex®-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC
  • Security:
  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm® TrustZone® based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI™ interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security co-processor (DMSC) for key and security management, with dedicated device level interconnect for security
  • SoC services:
  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)
  • Multimedia:
  • One Camera Serial Interface-2 (MIPI® CSI-2)
  • High-speed interfaces:
  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express® (PCIe®) revision 3.1 subsystems (1)
    • Supports Gen3 (8.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and/or end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (1)
    • One enhanced SuperSpeed Gen1 Port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB dual-role device
  • General connectivity:
  • 6× Inter-Integrated Circuit (I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins
  • Control interfaces:
  • 6× Enhanced High Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • Automotive interfaces:
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Audio interfaces:
  • 3× Multichannel Audio Serial Port (MCASP) modules
  • Media and data storage:
  • 2× MultiMedia Card/Secure Digital® (MMC™/SD®) interfaces
  • Simplified power management:
  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients
  • Analog/system integration:
  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change
  • System-on-Chip (SoC) architecture:
  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

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Parametrics

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Part number Order Arm CPU Arm MHz (Max.) DRAM Co-processor(s) EMIF Other on-chip memory Ethernet MAC Serial I/O Storage interface PCIe McASP Security enabler USB
DRA80M Order now 4 Arm Cortex-A53     1100
1000
800    
DDR3L-1600
DDR4-1600
LPDDR4-1333    
Arm Cortex-R5F PRU-ICSS     1x 39-bit with ECC     2.5 MB     10/100/1000
6-Port 10/100/1000 PRU EMAC    
CAN-FD
I2C
SPI
UART
USB    
1x SDIO 4b
1x SDIO 8b
1x UHSI 4b
1x eMMC 8b    
2 PCIe Gen3     3     Cryptographic acceleration
Debug security
Device identity
Secure boot
Trusted execution environment    
1 USB2.0
1 USB3.0