SLVSDJ3B February 2017  – December 2017 DRV8320 , DRV8320R , DRV8323 , DRV8323R


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6SPI Timing Requirements
    7. 7.7Typical Characteristics
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Three Phase Smart Gate Drivers
        1. Control Modes
          1. PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. Interface Modes
          1. Peripheral Interface (SPI)
          2. Interface
        3. Driver Voltage Supplies
        4. Gate Drive Architecture
          1. MOSFET Slew-Rate Control
          2. MOSFET Gate Drive Control
          3. Delay
          4. VDS Monitors
          5. Sense Pin
      2. 8.3.2DVDD Linear Voltage Regulator
      3. 8.3.3Pin Diagrams
      4. 8.3.4Low-Side Current Sense Amplifiers (DRV8323 and DRV8323R Only)
        1. Current Sense Operation
        2. Current Sense Operation (SPI only)
        3. Offset Calibration
        4. VDS Sense Mode (SPI Only)
      5. 8.3.5Step-Down Buck Regulator
        1. Frequency PWM Control
        2. Voltage (CB)
        3. Voltage Setting
        4. nSHDN and VIN Undervoltage Lockout
        5. Limit
        6. Transient Protection
        7. Shutdown
      6. 8.3.6Gate Driver Protective Circuits
        1. Supply Undervoltage Lockout (UVLO)
        2. Charge Pump Undervoltage Lockout (CPUV)
        3. VDS Overcurrent Protection (VDS_OCP)
          1. Latched Shutdown (OCP_MODE = 00b)
          2. Automatic Retry (OCP_MODE = 01b)
          3. Report Only (OCP_MODE = 10b)
          4. Disabled (OCP_MODE = 11b)
        4. Overcurrent Protection (SEN_OCP)
          1. Latched Shutdown (OCP_MODE = 00b)
          2. Automatic Retry (OCP_MODE = 01b)
          3. Report Only (OCP_MODE = 10b)
          4. Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. Driver Fault (GDF)
        6. Warning (OTW)
        7. Shutdown (OTSD)
    4. 8.4Device Functional Modes
      1. 8.4.1Gate Driver Functional Modes
        1. Mode
        2. Mode
        3. Reset (CLR_FLT or ENABLE Reset Pulse)
      2. 8.4.2Buck Regulator Functional Modes
        1. Conduction Mode (CCM)
        2. Control Scheme
    5. 8.5Programming
      1. 8.5.1SPI Communication
          1. Format
    6. 8.6Register Maps
      1. 8.6.1Status Registers
        1. Status Register 1 (address = 0x00)
        2. Status Register 2 (address = 0x01)
      2. 8.6.2Control Registers
        1. Control Register (address = 0x02)
        2. Drive HS Register (address = 0x03)
        3. Drive LS Register (address = 0x04)
        4. Control Register (address = 0x05)
        5. Control Register (DRV8323x Only) (address = 0x06)
  9. Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Primary Application
        1. Requirements
        2. Design Procedure
          1. MOSFET Support
          2. Configuration
          3. Overcurrent Monitor Configuration
          4. Amplifier Bidirectional Configuration (DRV8323 and DRV8323R)
          5. Regulator Configuration (DRV8320R and DRV8323R)
        3. Curves
      2. 9.2.2Alternative Application
        1. Requirements
        2. Design Procedure
          1. Amplifier Unidirectional Configuration
  10. 10Power Supply Recommendations
    1. 10.1Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1Buck-Regulator Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Device Support
      1. 12.1.1Device Nomenclature
    2. 12.2Documentation Support
      1. 12.2.1Related Documentation
    3. 12.3Related Links
    4. 12.4Receiving Notification of Documentation Updates
    5. 12.5Community Resources
    6. 12.6Trademarks
    7. 12.7Electrostatic Discharge Caution
    8. 12.8Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information


  • Triple Half-Bridge Gate Driver
    • Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
  • Smart Gate Drive Architecture
    • Adjustable Slew Rate Control
    • 10-mA to 1-A Peak Source Current
    • 20-mA to 2-A Peak Sink Current
  • Integrated Gate Driver Power Supplies
    • Supports 100% PWM Duty Cycle
    • High-Side Charge Pump
    • Low-Side Linear Regulator
  • 6 to 60-V Operating Voltage Range
  • Optional Integrated Buck Regulator
    • 4 to 60-V Operating Voltage Range
    • 0.8 to 60-V, 600-mA Output Capability
  • Optional Integrated Triple Current Sense Amplifiers (CSAs)
    • Adjustable Gain (5, 10, 20, 40 V/V)
    • Bidirectional or Unidirectional Support
  • SPI and Hardware Interface Available
  • 6x, 3x, 1x, and Independent PWM Modes
  • Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
  • Low-Power Sleep Mode (12 µA)
  • Linear Voltage Regulator, 3.3 V, 30 mA
  • Compact QFN Packages and Footprints
  • Efficient System Design With Power Blocks
  • Integrated Protection Features
    • VM Undervoltage Lockout (UVLO)
    • Charge Pump Undervoltage (CPUV)
    • MOSFET Overcurrent Protection (OCP)
    • Gate Driver Fault (GDF)
    • Thermal Warning and Shutdown (OTW/OTSD)
    • Fault Condition Indicator (nFAULT)


  • Brushless-DC (BLDC) Motor Modules
  • Fans and Pumps
  • E-Bikes, E-Scooters, and E-Mobility
  • Cordless Garden and Power Tools
  • Cordless Vacuum Cleaners
  • Drones, Robotics, and RC Toys
  • ATM and Currency Counting


The DRV832x family of devices is an integrated gate driver for three-phase applications. The devices provide three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The DRV832x generates the correct gate drive voltages using an integrated charge pump for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV832x can operate from a single power supply and supports a wide input supply range of 6 to 60 V for the gate driver and 4 to 60 V for the optional buck regulator.

The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface. The DRV8323 and DRV8323R devices integrate three low-side current sense amplifiers that allow bidirectional current sensing on all three phases of the drive stage. The DRV8320R and DRV8323R devices integrate a 600-mA buck regulator.

A low-power sleep mode is provided to achieve low quiescent current draw by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for for SPI device variants.

Device Information(1)

DRV8320WQFN (32)5.00 mm × 5.00 mm
DRV8320RVQFN (40)6.00 mm × 6.00 mm
DRV8323WQFN (40)6.00 mm × 6.00 mm
DRV8323RVQFN (48)7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

DRV8320 DRV8320R DRV8323 DRV8323R simp_sch_slvsdj3.gif

Revision History

Changes from A Revision (April 2017) to B Revision

  • Changed the low-power sleep mode supply current from the maximum value (20 µA) to the typical value (12 µA) in the FeaturesGo
  • Changed the ApplicationsGo
  • Changed the GAIN value from 45 kΩ to 47 kΩ in the test condition of the amplifier gain for the H/W device in the Electrical Characteristics tableGo
  • Deleted tEN_nSCS from the SPI Slave Mode Timing DiagramGo
  • Added a note to the Synchronous 1x PWM Mode to define !PWMGo
  • Updated the Auto Offset Calibration sectionGo
  • Updated the VDS Latched Shutdown and VDS Automatic Retry sectionsGo
  • Updated the Sleep Mode sectionGo
  • Changed the address listed in the title for the Gate Drive LS Register section to the correct register address, 0x04Go
  • Changed the maximum Qg value for both trapezoidal and sinusoidal commutation the VVM = 8 V example of the Detailed Design ProcedureGo
  • Changed IDRIVEP and IDRIVEN equations in the IDRIVE Configuration sectionGo

Changes from * Revision (February 2017) to A Revision

  • Changed the test condition for the IBIAS parameter in the Electrical Characteristics tableGo
  • Changed the GHx values in the 3x PWM Mode Truth TableGo
  • Changed the calibration description and added auto calibration feature description Go