Home Interface High-speed SerDes FPD-Link SerDes

DS90CF366

ACTIVE

+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz

Product details

Function Deserializer Color depth (bps) 18 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
Function Deserializer Color depth (bps) 18 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 20-MHz to 85-MHz Shift Clock Support
  • Rx Power Consumption <142 mW (Typical) at
    85-MHz Grayscale
  • Rx Power-Down Mode <1.44 mW (Maximum)
  • ESD Rating >7 kV (HBM), >700 V (EIAJ)
  • Supports VGA, SVGA, XGA, and Single Pixel
    SXGA
  • PLL Requires No External Components
  • Compatible With TIA/EIA-644 LVDS Standard
  • Low Profile 56-Pin or 48-Pin TSSOP Package
  • DS90CF386 Also Available in a 64-Pin, 0.8-mm,
    Fine Pitch Ball Grid Array (NFBGA) Package
  • 20-MHz to 85-MHz Shift Clock Support
  • Rx Power Consumption <142 mW (Typical) at
    85-MHz Grayscale
  • Rx Power-Down Mode <1.44 mW (Maximum)
  • ESD Rating >7 kV (HBM), >700 V (EIAJ)
  • Supports VGA, SVGA, XGA, and Single Pixel
    SXGA
  • PLL Requires No External Components
  • Compatible With TIA/EIA-644 LVDS Standard
  • Low Profile 56-Pin or 48-Pin TSSOP Package
  • DS90CF386 Also Available in a 64-Pin, 0.8-mm,
    Fine Pitch Ball Grid Array (NFBGA) Package

The DS90CF386 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CF366 receiver that converts three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the falling edge. A rising edge or falling edge strobe transmitter will interoperate with a falling edge strobe receiver without any translation logic.

The receiver LVDS clock operates at rates from 20 MHz to 85 MHz. The device phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 85 MHz, each LVDS input line is running at a bit rate of 595 Mbps, resulting in a maximum throughput of 2.38 Gbps for the DS90CF386 and 1.785 Gbps for the DS90CF366.

The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high-speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages. The DS90CF386 is also offered in a 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA) package which provides a 44% reduction in PCB footprint compared to the 56-pin TSSOP package.

The DS90CF386 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CF366 receiver that converts three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the falling edge. A rising edge or falling edge strobe transmitter will interoperate with a falling edge strobe receiver without any translation logic.

The receiver LVDS clock operates at rates from 20 MHz to 85 MHz. The device phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 85 MHz, each LVDS input line is running at a bit rate of 595 Mbps, resulting in a maximum throughput of 2.38 Gbps for the DS90CF386 and 1.785 Gbps for the DS90CF366.

The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high-speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages. The DS90CF386 is also offered in a 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA) package which provides a 44% reduction in PCB footprint compared to the 56-pin TSSOP package.

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Technical documentation

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Type Title Date
* Data sheet DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz datasheet (Rev. J) PDF | HTML 31 May 2016
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29 Jun 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 08 Aug 2017
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 Jan 2016
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15 May 2004
Application note AN-1056 STN Application Using FPD-Link 14 May 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14 May 2004

Design & development

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Evaluation board

FLINK3V8BT-85 — Evaluation kit for FPD-Link family of serializer and deserializer LVDS devices

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

User guide: PDF
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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TSSOP (DGG) 48 View options

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