DS90CR285

ACTIVE

+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Transmitter - 66 MHz

Product details

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Single +3.3V Supply
  • Chipset (Tx + Rx) Power Consumption <250 mW (typ)
  • Power-Down Mode (<0.5 mW total)
  • Up to 231 Megabytes/sec Bandwidth
  • Up to 1.848 Gbps Data Throughput
  • Narrow Bus Reduces Cable Size
  • 290 mV Swing LVDS Devices for Low EMI
  • +1V Common Mode Range (Around +1.2V)
  • PLL Requires no External Components
  • Both Devices are Offered in a Low Profile 56-Lead TSSOP Package
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 7 kV
  • Operating Temperature: −40°C to +85°C

All trademarks are the property of their respective owners.

  • Single +3.3V Supply
  • Chipset (Tx + Rx) Power Consumption <250 mW (typ)
  • Power-Down Mode (<0.5 mW total)
  • Up to 231 Megabytes/sec Bandwidth
  • Up to 1.848 Gbps Data Throughput
  • Narrow Bus Reduces Cable Size
  • 290 mV Swing LVDS Devices for Low EMI
  • +1V Common Mode Range (Around +1.2V)
  • PLL Requires no External Components
  • Both Devices are Offered in a Low Profile 56-Lead TSSOP Package
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 7 kV
  • Operating Temperature: −40°C to +85°C

All trademarks are the property of their respective owners.

The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR286 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s).

The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.

The 28 LVCMOS/LVTTL inputs can support a variety of signal combinations. For example, seven 4-bit nibbles or three 9-bit (byte + parity) and 1 control.

The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR286 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s).

The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.

The 28 LVCMOS/LVTTL inputs can support a variety of signal combinations. For example, seven 4-bit nibbles or three 9-bit (byte + parity) and 1 control.

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Technical documentation

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Type Title Date
* Data sheet DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28Bit Channel Link- 66MHz datasheet (Rev. C) 05 Mar 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) 03 Aug 2018
EVM User's guide DS90CR285-86ATQEVM User's Guide 22 Aug 2016
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 Jan 2016
Application note Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A) 26 Apr 2013
Design guide Channel Link I Design Guide 29 Mar 2007
Application note Multi-Drop Channel-Link Operation 04 Oct 2004
Application note CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications 05 Oct 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DS90CR285-86ATQEVM — DS90CR285 and DS90CR286AT-Q1 Channel Link I SerDes Evaluation Module

The DS90CR285-86ATQEVM contains a Transmitter (Tx) board, a Receiver (Rx) board, and interfacing cables. This kit allows users to interface from test equipment or a graphics controller through Low Voltage Differential Signaling (LVDS) to a receiver board. The DS90CR285-86ATQEVM can be used for (...)
User guide: PDF
Not available on TI.com
Evaluation board

FLINK3V8BT-85 — Evaluation kit for FPD-Link family of serializer and deserializer LVDS devices

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

User guide: PDF
Not available on TI.com
Simulation model

DS90CR285 IBIS Model

SNLM037.ZIP (4 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins Download
TSSOP (DGG) 56 View options

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