Home Interface LVDS, M-LVDS & PECL ICs
Home
Interface
LVDS, M-LVDS & PECL ICs

DS90LV028AQ-Q1

ACTIVE

Automotive LVDS dual differential line receiver

Order now
Data sheet

DS90LV028AQ-Q1

ACTIVE
Data sheet Order now

Product details

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDS Output signal LVTTL, TTL Rating Automotive Operating temperature range (°C) -40 to 125
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDS Output signal LVTTL, TTL Rating Automotive Operating temperature range (°C) -40 to 125
SOIC (D) 8 29.4 mm² 4.9 x 6
  • AECQ-100 Qualified for Automotive Applications
    • Temperature Grade 1: -40°C to +125°C TA
  • >400 Mbps (200 MHz) Switching Rates
  • 50 ps Differential Skew (Typical)
  • 0.1 ns Channel-to-Channel Skew (Typical)
  • 2.5 ns Maximum Propagation Delay
  • 3.3V Power Supply Design
  • Flow-Through Pinout
  • Power Down High Impedance on LVDS Inputs
  • Low Power design (18 mW at 3.3 V static)
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Conforms to ANSI/TIA/EIA-644 Standard
  • Available in SOIC Package
  • AECQ-100 Qualified for Automotive Applications
    • Temperature Grade 1: -40°C to +125°C TA
  • >400 Mbps (200 MHz) Switching Rates
  • 50 ps Differential Skew (Typical)
  • 0.1 ns Channel-to-Channel Skew (Typical)
  • 2.5 ns Maximum Propagation Delay
  • 3.3V Power Supply Design
  • Flow-Through Pinout
  • Power Down High Impedance on LVDS Inputs
  • Low Power design (18 mW at 3.3 V static)
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Conforms to ANSI/TIA/EIA-644 Standard
  • Available in SOIC Package

The DS90LV028AQ is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV028AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3 V CMOS output levels. The DS90LV028AQ has a flow-through design for easy PCB layout.

The DS90LV028AQ and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

The DS90LV028AQ is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV028AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3 V CMOS output levels. The DS90LV028AQ has a flow-through design for easy PCB layout.

The DS90LV028AQ and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.
open-in-new Find other LVDS, M-LVDS & PECL ICs
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device
DS90LV028A-Q1 ACTIVE Automotive LVDS dual differential line receiver This product offers the same functionality in a 79% smaller package.

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 5
Type Title Date
* Data sheet DS90LV028AQ-Q1 Automotive LVDS Dual Differential Line Receiver datasheet (Rev. I) PDF | HTML 22 Jun 2020
Application brief LVDS to Improve EMC in Motor Drives 27 Sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 Aug 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 May 2018
Application note An Overview of LVDS Technology 05 Oct 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DS90LV027A-28AEVM — Dual channel LVDS driver and receiver evaluation module

The DS90LV027A-28A is an evaluation module designed for performance and functional evaluation of the Texas Instruments DS90LV027A LVDS dual  differential driver and DS90LV028A LVDS dual differential line receiver. With this kit, users can quickly evaluate the output waveform characteristics (...)
Not available on TI.com
Simulation model

DS90LV028A IBIS Model

SNLM018.ZIP (4 KB) - IBIS Model
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
View options
Reference designs

TIDA-01021 — Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers

High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01022 — Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01023 — High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01024 — High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01027 — Low-noise power supply reference design maximizing performance in 12.8-GSPS data acquisition systems

This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01028 — 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-010128 — Scalable 20.8 GSPS reference design for 12 bit digitizers

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-010122 — Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems

This reference design addresses synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array radar and communication payload. The typical RF front end contains antenna, low-noise amplifier (LNA), mixer, local (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-010132 — Multichannel RF transceiver reference design for radar and electronic warfare applications

This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-010131 — Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers

Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
SOIC (D) 8 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos