The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus.
There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period.
Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package.
|Color Depth (bpp)|
|Pixel Clock Min (MHz)|
|Pixel Clock (Max) (MHz)|
|Total Throughput (Mbps)|
|Operating Temperature Range (C)|
|Package Size: mm2:W x L (PKG)|
|FPD-Link III LVDS||LVCMOS||FPD-Link III LVDS||LVCMOS||FPD-Link III LVDS||LVCMOS|
|LVCMOS||FPD-Link III LVDS||LVCMOS||FPD-Link III LVDS||LVCMOS||FPD-Link III LVDS|
| 2:1 input multiplexer |
| CRC |
| CRC |
|I2C Config||I2C Config|| CRC |
|Adaptive Equalizer||-||Programmable Equalizer||-||Programmable Equalizer||-|
| SSCG |
|-|| SSCG |
|-|| SSCG |
|-40 to 105||-40 to 105||-40 to 105||-40 to 105||-40 to 105||-40 to 105|
|48WQFN: 49 mm2: 7 x 7(WQFN)||32WQFN: 25 mm2: 5 x 5(WQFN)||40WQFN: 36 mm2: 6 x 6(WQFN)||40WQFN: 36 mm2: 6 x 6(WQFN)||48WQFN: 49 mm2: 7 x 7(WQFN)||32WQFN: 25 mm2: 5 x 5(WQFN)|
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