SNLS440C MARCH 2013  – July 2016 DS90UH928Q-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Timing Requirements for the Serial Control Bus
    8. 6.8 Timing Requirements
    9. 6.9 DC and AC Serial Control Bus Characteristics
    10. 6.10Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 High Speed Forward Channel Data Transfer
      2. 7.3.2 Low-Speed Back Channel Data Transfer
      3. 7.3.3 Backward Compatible Mode
      4. 7.3.4 Input Equalization
      5. 7.3.5 Common Mode Filter Pin (CMF)
      6. 7.3.6 Power Down (PDB)
      7. 7.3.7 Video Control Signals
      8. 7.3.8 EMI Reduction Features
        1. 7.3.8.1LVCMOS VDDIO Option
      9. 7.3.9 Built In Self Test (BIST)
        1. 7.3.9.1BIST Configuration and Status
          1. 7.3.9.1.1Sample BIST Sequence
        2. 7.3.9.2Forward Channel and Back Channel Error Checking
      10. 7.3.10Internal Pattern Generation
        1. 7.3.10.1Pattern Options
        2. 7.3.10.2Color Modes
        3. 7.3.10.3Video Timing Modes
        4. 7.3.10.4External Timing
        5. 7.3.10.5Pattern Inversion
        6. 7.3.10.6Auto Scrolling
        7. 7.3.10.7Additional Features
      11. 7.3.11Image Enhancement Features
        1. 7.3.11.1White Balance
          1. 7.3.11.1.1LUT Contents
          2. 7.3.11.1.2Enabling White Balance
        2. 7.3.11.2Adaptive Hi-FRC Dithering
      12. 7.3.12Serial Link Fault Detect
      13. 7.3.13Oscillator Output
      14. 7.3.14Interrupt Pin (INTB / INTB_IN)
      15. 7.3.15General-Purpose I/O
        1. 7.3.15.1GPIO[3:0]
        2. 7.3.15.2GPIO[8:5]
      16. 7.3.16I2S Audio Interface
        1. 7.3.16.1I2S Transport Modes
        2. 7.3.16.2I2S Repeater
        3. 7.3.16.3I2S Jitter Cleaning
        4. 7.3.16.4MCLK
    4. 7.4Device Functional Modes
      1. 7.4.1Clock and Output Status
      2. 7.4.2FPD-Link Input Frame and Color Bit Mapping Select
      3. 7.4.3Low Frequency Optimization (LFMODE)
      4. 7.4.4Mode Select (MODE_SEL)
      5. 7.4.5Repeater Connections
        1. 7.4.5.1Repeater Fan-Out Electrical Requirements
      6. 7.4.6HDCP I2S Audio Encryption
      7. 7.4.7Repeater Configuration
    5. 7.5Programming
      1. 7.5.1Serial Control Bus
    6. 7.6Register Maps
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. 8.2.2.1Transmission Media
        2. 8.2.2.2Display Application
      3. 8.2.3Application Curves
    3. 8.3AV Mute PreventionAV Mute Prevention section.
    4. 8.4OEN Toggling LimitationOEN Toggling Limitation.
  9. Power Supply Recommendations
    1. 9.1Power Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1Layout Guidelines
      1. 10.1.1CML Interconnect Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications AEC-Q100
    • Device Temperature Grade 2: -40°C to +105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level ±8 kV
    • Device CDM ESD Classification Level C6
  • Integrated HDCP Cipher Engine with On-Chip Key Storage
  • Supports HDCP Repeater Application
  • Bidirectional Control Channel Interface with I2C Compatible Serial Control Bus
  • Low EMI FPD-Link Video Output
  • Supports High Definition (720p) Digital Video
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • 5 MHz to 85 MHz Pixel Clock Support
  • Up to 4 I2S Digital Audio Outputs for Surround Sound Applications
  • 4 Bidirectional GPIO Channels with 2 Dedicated Pins
  • Single 3.3 V supply with 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
  • AC-Coupled STP Interconnect Up to 10 Meters
  • DC-Balanced and Scrambled Data with Embedded Clock
  • Adaptive Cable Equalization
  • Image Enhancement (White Balance & Dithering) and Internal Pattern Generation
  • Backward Compatible Modes

2 Applications

  • Automotive Displays for Navigation
  • Rear Seat Entertainment Systems

3 Description

The DS90UH928Q-Q1 deserializer, in conjunction with a DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI (FPD-Link)), and I2S audio data. The digital video and audio data is protected using the industry standard HDCP copy protection scheme.The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.

The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
DS90UH928Q-Q1WQFN (48)7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Application Diagram

DS90UH928Q-Q1 DS90UH928Q_TYP_APP.gif