SNLS440C MARCH   2013  – July 2016 DS90UH928Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Timing Requirements
    9. 6.9  DC and AC Serial Control Bus Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization
      5. 7.3.5  Common Mode Filter Pin (CMF)
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Video Control Signals
      8. 7.3.8  EMI Reduction Features
        1. 7.3.8.1 LVCMOS VDDIO Option
      9. 7.3.9  Built In Self Test (BIST)
        1. 7.3.9.1 BIST Configuration and Status
          1. 7.3.9.1.1 Sample BIST Sequence
        2. 7.3.9.2 Forward Channel and Back Channel Error Checking
      10. 7.3.10 Internal Pattern Generation
        1. 7.3.10.1 Pattern Options
        2. 7.3.10.2 Color Modes
        3. 7.3.10.3 Video Timing Modes
        4. 7.3.10.4 External Timing
        5. 7.3.10.5 Pattern Inversion
        6. 7.3.10.6 Auto Scrolling
        7. 7.3.10.7 Additional Features
      11. 7.3.11 Image Enhancement Features
        1. 7.3.11.1 White Balance
          1. 7.3.11.1.1 LUT Contents
          2. 7.3.11.1.2 Enabling White Balance
        2. 7.3.11.2 Adaptive Hi-FRC Dithering
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Interrupt Pin (INTB / INTB_IN)
      15. 7.3.15 General-Purpose I/O
        1. 7.3.15.1 GPIO[3:0]
        2. 7.3.15.2 GPIO[8:5]
      16. 7.3.16 I2S Audio Interface
        1. 7.3.16.1 I2S Transport Modes
        2. 7.3.16.2 I2S Repeater
        3. 7.3.16.3 I2S Jitter Cleaning
        4. 7.3.16.4 MCLK
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock and Output Status
      2. 7.4.2 FPD-Link Input Frame and Color Bit Mapping Select
      3. 7.4.3 Low Frequency Optimization (LFMODE)
      4. 7.4.4 Mode Select (MODE_SEL)
      5. 7.4.5 Repeater Connections
        1. 7.4.5.1 Repeater Fan-Out Electrical Requirements
      6. 7.4.6 HDCP I2S Audio Encryption
      7. 7.4.7 Repeater Configuration
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
        2. 8.2.2.2 Display Application
      3. 8.2.3 Application Curves
    3. 8.3 AV Mute PreventionAV Mute Prevention section.
    4. 8.4 OEN Toggling LimitationOEN Toggling Limitation.
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90UH928Q-Q1 deserializer, in conjunction with a DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video and audio within automotive infotainment systems. It converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (FPD-Link), and I2S audio data. The digital video and audio data is protected using the industry standard HDCP copy protection scheme.The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

8.2 Typical Application

Figure 39 shows a typical application of the DS90UH928Q-Q1 deserializer for an 85 MHz 24-bit color display application. Inputs utilize 0.1 µF coupling capacitors to the line, and the deserializer provides internal termination. The voltage rating of the coupling capacitors must be ≥50 V and use a small body capacitor size, such as 0402 or 0602, to help ensure good signal integrity. The FPD-Link LVDS differential outputs require 100 Ω termination resistors at the receiving device or display.

Bypass capacitors must be placed near the power supply pins. At a minimum, three 4.7 μF capacitors, one placed at each power supply pin, are required for local device bypassing. If additional bypass capacitors are used, place the smaller value components closer to the pin. Ferrite beads are required on the two supplies (VDD33 and VDDIO) for effective noise suppression. Connect pins VDD33_A and VDD33_B directly to ensure ESD performance. The interface to the display is FPD-Link LVDS. The VDDIO pin may be connected to 3.3 V or 1.8 V. Place a delay capacitor (>10 µF) and pullup resistor (10 kΩ) on the PDB signal to delay the enabling of the device until power is stable.

DS90UH928Q-Q1 TYP_CONN.gif Figure 39. Typical Connection Diagram
DS90UH928Q-Q1 DS90UH928Q_TYP_APP.gif Figure 40. Typical Display System Diagram

8.2.1 Design Requirements

For the typical design application, use the following as input parameters:

Table 9. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDDIO 1.8 V or 3.3 V
VDD33 3.3 V
AC Coupling Capacitor for RIN± 100 nF
PCLK Frequency 78 MHz

8.2.2 Detailed Design Procedure

8.2.2.1 Transmission Media

The DS90UH927Q-Q1 and DS90UH928Q-Q1 chipset is intended to be used in a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer must have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, and so forth.) and the application environment.

The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define the acceptable data eye opening width (EW) and eye opening height (EH). A differential probe should be used to measure across the termination resistor of 100 Ω between the CMLOUTP and CMLOUTN pins.

8.2.2.2 Display Application

The DS90UH928Q-Q1, in conjunction with the DS90UH925Q-Q1 or DS90UH927Q-Q1, is intended for interfacing with a HDCP compliant host (graphics processor) and a display supporting 24-bit color depth (RGB888) and high-definition (720p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz together with three control bits (VS, HS, and DE) and four I2S audio streams. The included HDCP 1.3 compliant cipher block allows the authentication of the HDCP Deserializer, which decrypts both video and audio contents. The HDCP keys are pre-loaded by TI into Non-Volatile Memory (NVM) for maximum security.

8.2.3 Application Curves

DS90UH928Q-Q1 78delay.gif Figure 41. 78-MHz Clock at Serializer and Deserializer
DS90UH928Q-Q1 48cmlout.gif Figure 42. CMLOUT of Deserializer from 48 MHz Input Clock

8.3 AV Mute Prevention

The DS90UH928Q-Q1 may inadvertently enter the AV MUTE state if the serializer sends video data during blanking period (DE = L) with a specific data pattern (24’h666666). Once the device enters the AV MUTE state, the device mutes both audio and video outputs resulting in a black display screen. Setting the gate DE Register 0x04[4] on the serializer will prevent video signals from being sent during the blanking interval. This will ensure AV MUTE mode is not entered during normal operation.

If unexpected AV MUTE state is seen, it is recommended to verify checking the data path control setting of the paired Serializer. This setting is not accessible from DS90UH928Q-Q1.

8.4 OEN Toggling Limitation

EON should be enabled LVDS outputs after PDB turns to high state and the internal circuit is stabled. Since OEN function is asynchronous signal to the internal digital blocks, repeated by OEN toggling may result in horizontal pixel shift at the LVDS output. TO avoid this, recommend to reset by programming Register 0x01[0] for digital blocks after OEN turn to ON state.