DSLVDS1048 3.3-V LVDS Quad Channel High-Speed Differential Line Receiver | TI.com

DSLVDS1048 (ACTIVE)

3.3-V LVDS Quad Channel High-Speed Differential Line Receiver

 

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Description

The DSLVDS1048 device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.

The DSLVDS1048 accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DSLVDS1048 has a flow-through pinout for easy PCB layout.

The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DSLVDS1048 and companion LVDS line driver (for example, DSLVDS1047) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.

Features

  • Designed for Signal Rates up to 400 Mbps
  • Flow-Through Pinout Simplifies PCB Layout
  • 150-ps Channel-to-Channel Skew (Typical)
  • 100-ps Differential Skew (Typical)
  • 2.7-ns Maximum Propagation Delay
  • 3.3-V Power Supply Design
  • High Impedance LVDS Inputs on Power Down
  • Low Power Design (40 mW at 3.3-V Static)
  • Interoperable With Existing 5-V LVDS Drivers
  • Accepts Small Swing (350 mV Typical) Differential Signal Levels
  • Supports Input Failsafe
    • Open, Short, and Terminated
  • 0 V to −100 mV Threshold Region
  • Operating Temperature Range: –40°C to +85°C
  • Meets or Exceeds ANSI/TIA/EIA-644 Standard
  • Available in TSSOP Package

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Parametrics Compare all products in Buffers, drivers/receivers & cross-points

 
Device type
Protocols
Number of Tx
Number of Rx
Input signal
Output signal
Signaling Rate (Mbps)
ESD HBM (kV)
Function
Operating temperature range (C)
Package Group
Package size: mm2:W x L (PKG)
DSLVDS1048 DS90C031 DS90C031B DS90C032 DS90C032B DS90LV031A DS90LV032A DS90LV048A DSLVDS1047 SN65LVDS047 SN65LVDS048A SN65LVDS349 SN65LVDS352
Receiver     Driver     Driver     Receiver     Receiver     Driver     Receiver     Receiver     Driver     Driver     Receiver     Receiver     Receiver    
LVDS     LVDS     LVDS     LVDS     LVDS     LVDS     LVDS     LVDS     LVDS     LVDS     LVDS     LVDS     LVDS    
0     4     4     4     0     4     0     0     4     4     0     0     0    
4     0     0     4     4     0     4     4     0     0     4     4     4    
LVDS     TTL
CMOS    
TTL
CMOS    
LVDS     LVDS     LVTTL
LVCMOS    
LVDS     LVDS     TTL
LVTTL
CMOS    
TTL
LVTTL
CMOS    
LVDS     CMOS
ECL
LVCMOS
LVDS
LVECL
LVPECL
PECL    
CMOS
ECL
LVCMOS
LVDS
LVECL
LVPECL
PECL    
TTL
LVTTL    
LVDS     LVDS     TTL     TTL     LVDS     LVCMOS     TTL
LVTTL    
LVDS     LVDS     TTL
LVTTL    
LVTTL     LVTTL    
400     155.5     155.5     155.5     155.5     400     400     400     400     400     400     560     560    
10     3.5     2     3.5     2     6     4.5     10     1.2     10     10     15     15    
Receiver     Driver     Driver     Receiver     Receiver     Driver     Receiver     Receiver     Driver     Driver     Receiver     Receiver     Receiver    
-40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85    
TSSOP | 16     SOIC | 16     SOIC | 16     SOIC | 16     SOIC | 16     SOIC | 16
TSSOP | 16    
SOIC | 16
TSSOP | 16