SLVSE49A July   2017  – July 2017 ESD401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings — JEDEC Specification 
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 ESD Protection
      2. 7.3.2 IEC 61000-4-4 EFT Protection
      3. 7.3.3 IEC 61000-4-5 Surge Protection
      4. 7.3.4 IO Capacitance
      5. 7.3.5 DC Breakdown Voltage
      6. 7.3.6 Low Leakage Current
      7. 7.3.7 Low ESD Clamping Voltage
      8. 7.3.8 Industrial Temperature Range
      9. 7.3.9 Industry Standard Footprint
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The ESD401 is a bidirectional ESD Protection Diode with ultra-low clamping voltage. This device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low clamping makes this device ideal for protecting any sensitive signal pins.

7.2 Functional Block Diagram

ESD401 esd401-functional-block-diagram.gif

7.3 Feature Description

7.3.1 IEC 61000-4-2 ESD Protection

The I/O pins can withstand ESD events up to ±24-kV contact and ±30-kV air gap. An ESD-surge clamp diverts the current to ground.

7.3.2 IEC 61000-4-4 EFT Protection

The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω impedance). An ESD-surge clamp diverts the current to ground.

7.3.3 IEC 61000-4-5 Surge Protection

The I/O pins can withstand surge events up to 4.5 A and 67W (8/20 µs waveform). An ESD-surge clamp diverts this current to ground.

7.3.4 IO Capacitance

The capacitance between each I/O pin to ground is 0.77 pF (typical) and 0.95 pF (maximum).

7.3.5 DC Breakdown Voltage

The DC breakdown voltage of each I/O pin is ±8.3 V typical. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of ±5.5 V.

7.3.6 Low Leakage Current

The I/O pins feature an low leakage current of 10 nA (maximum) with a bias of ±2.5 V.

7.3.7 Low ESD Clamping Voltage

The I/O pins feature an ESD clamp that is capable of clamping the voltage to 24 V (TLP IPP = 16 A).

7.3.8 Industrial Temperature Range

This device features an industrial operating range of –40°C to +125°C.

7.3.9 Industry Standard Footprint

The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout.

7.4 Device Functional Modes

The ESD401 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During ESD events, voltages as high as ±24 kV (contact) or ±30 kV ( air) can be directed to ground via the internal diode network. When the voltages on the protected line fall below the trigger levels of ESD401 (usually within 10s of nano-seconds) the device reverts to passive.

Figure 11 shows typical TLP behavior of bi-directional ESD device that does not exhibit snapback.

ESD401 Generic_TLP_Curve_non_snapback.gif Figure 11. Typical TlpLP Behavior Of Bi-directional ESD Device that Does Not Exhibit Snapback