SBOS547A June 2011  – August 2015 INA226

PRODUCTION DATA. 
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Typical Characteristics
  7. 7 Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Basic ADC Functions
        1. 7.3.1.1Power Calculation
        2. 7.3.1.2Alert Pin
    4. 7.4Device Functional Modes
      1. 7.4.1Averaging and Conversion Time Considerations
      2. 7.4.2Filtering and Input Considerations
    5. 7.5Programming
      1. 7.5.1Programming the Calibration Register
      2. 7.5.2Programming the Power Measurement Engine
        1. 7.5.2.1Calibration Register and Scaling
      3. 7.5.3Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 7.5.4Default Settings
      5. 7.5.5Bus Overview
        1. 7.5.5.1Serial Bus Address
        2. 7.5.5.2Serial Interface
        3. 7.5.5.3Writing to and Reading from the INA226
          1. 7.5.5.3.1High-Speed I2C Mode
        4. 7.5.5.4SMBus Alert Response
    6. 7.6Register Maps
      1. 7.6.1 Configuration Register (00h) (Read/Write)
      2. 7.6.2 Shunt Voltage Register (01h) (Read-Only)
      3. 7.6.3 Bus Voltage Register (02h) (Read-Only)
      4. 7.6.4 Power Register (03h) (Read-Only)
      5. 7.6.5 Current Register (04h) (Read-Only)
      6. 7.6.6 Calibration Register (05h) (Read/Write)
      7. 7.6.7 Mask/Enable Register (06h) (Read/Write)
      8. 7.6.8 Alert Limit Register (07h) (Read/Write)
      9. 7.6.9 Manufacturer ID Register (FEh) (Read-Only)
      10. 7.6.10Die ID Register (FFh) (Read-Only)
  8. 8 Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Applications
      1. 8.2.1High-Side Sensing Circuit Application
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
        3. 8.2.1.3Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Development Support
    2. 11.2Community Resources
    3. 11.3Trademarks
    4. 11.4Electrostatic Discharge Caution
    5. 11.5Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MINMAXUNIT
VVSSupply voltage 6V
Analog Inputs, IN+, IN– Differential (VIN+ – VIN-)(2)–4040V
Common-Mode (VIN+ + VIN-) / 2–0.340
VVBUS–0.340V
VSDAGND – 0.36V
VSCLGND – 0.3VVS + 0.3V
IINInput current into any pin5mA
IOUTOpen-drain digital output current10mA
TJJunction temperature150°C
TstgStorage temperature range –65150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) IN+ and IN– may have a differential voltage between –40 V and 40 V. However, the voltage at these pins must not exceed the range –0.3 V to 40 V.

6.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)±2500V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)±1000
Machine model (MM)±150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
VCMCommon-mode input voltage12V
VVSOperating supply voltage3.3V
TAOperating free-air temperature–40125°C

6.4 Thermal Information

THERMAL METRIC(1) INA226UNIT
DGS (VSSOP)
10 PINS
RθJAJunction-to-ambient thermal resistance171.4°C/W
RθJC(top)Junction-to-case (top) thermal resistance 42.9°C/W
RθJBJunction-to-board thermal resistance91.8°C/W
ψJTJunction-to-top characterization parameter1.5°C/W
ψJBJunction-to-board characterization parameter90.2°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistancen/a°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT
Shunt voltage input range–81.917581.92mV
Bus voltage input range(1)036V
CMRRCommon-mode rejection0 V ≤ VIN+ ≤ 36 V126140dB
VOSShunt offset voltage, RTI(2)±2.5±10μV
Shunt offset voltage, RTI(2) vs temperature–40°C ≤ TA ≤ 125°C0.020.1μV/°C
PSRRShunt offset voltage, RTI(2) vs Power supply2.7 V ≤ VS ≤ 5.5 V2.5μV/V
VOSBus offset voltage, RTI(2)±1.25±7.5mV
Bus offset voltage, RTI(2) vs temperature–40°C ≤ TA ≤ 125°C1040μV/°C
PSRRBus offset voltage, RTI(2) vs power supply0.5mV/V
IBInput bias current (IIN+, IIN– pins)10μA
VBUS input impedance830kΩ
Input leakage (3) (IN+ pin) + (IN– pin),
Power-down mode		0.10.5μA
DC ACCURACY
ADC native resolution16Bits
1 LSB step sizeShunt voltage2.5μV
Bus voltage1.25mV
Shunt voltage gain error0.02%0.1%
Shunt voltage gain error vs temperature–40°C ≤ TA ≤ 125°C1050ppm/°C
Bus voltage gain error0.02%0.1%
Bus voltage gain error vs temperature–40°C ≤ TA ≤ 125°C1050ppm/°C
Differential nonlinearity±0.1LSB
tCTADC conversion timeCT bit = 000140154μs
CT bit = 001204224
CT bit = 010332365
CT bit = 011588646
CT bit = 1001.11.21ms
CT bit = 1012.1162.328
CT bit = 1104.1564.572
CT bit = 1118.2449.068
SMBus
SMBus timeout(4)2835ms
DIGITAL INPUT/OUTPUT
Input capacitance3pF
Leakage input current0 V ≤ VSCL ≤ VVS ,
0 V ≤ VSDA ≤ VVS,
0 V ≤ VAlert ≤ VVS ,
0 V ≤ VA0 ≤ VVS ,
0 V ≤ VA1 ≤ VVS 		0.11μA
VIHHigh-level input voltage0.7×VVS6V
VILLow-level input voltage–0.50.3×VVSV
VOL Low-level output voltage, SDA, AlertIOL = 3 mA00.4V
Hysteresis500mV
POWER SUPPLY
Operating supply range2.75.5V
IQQuiescent current330420μA
Quiescent current, power-down (shutdown) mode0.52μA
VPORPower-on reset threshold2V
(1) While the input range is 36 V, the full-scale range of the ADC scaling is 40.96 V. See the Basic ADC Functions section. Do not apply more than 36 V.
(2) RTI = Referred-to-input.
(3) Input leakage is positive (current flowing into the pin) for the conditions shown at the top of this table. Negative leakage currents can occur under different input conditions.
(4) SMBus timeout in the INA226 resets the interface any time SCL is low for more than 28 ms.

6.6 Typical Characteristics

At TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted.
INA226 g001_bos547.png
Figure 1. Frequency Response
INA226 g003_bos547.png
Figure 3. Shunt Input Offset Voltage vs Temperature
INA226 tc_histo_shunt_input_gain_err_distrib_bos547.gif
Figure 5. Shunt Input Gain Error Production Distribution
INA226 g007_bos547.png
Figure 7. Shunt Input Gain Error vs Common-Mode Voltage
INA226 g010_bos547.png
Figure 9. Bus Input Offset Voltage vs Temperature
INA226 g013_bos547.png
Figure 11. Bus Input Gain Error vs Temperature
INA226 g016_bos547.png
Figure 13. Input Bias Current vs Temperature
INA226 g018_bos547.png
Figure 15. Active IQ vs Temperature
INA226 tc_active_iq_fqcy_bos547.gif
Figure 17. Active IQ vs I2C Clock Frequency
INA226 tc_histo_shunt_input_offset_v_distrib_bos547.gif
Figure 2. Shunt Input Offset Voltage Production Distribution
INA226 g004_bos547.png
Figure 4. Shunt Input Common-Mode Rejection Ratio vs Temperature
INA226 g006_new_bos547.png
Figure 6. Shunt Input Gain Error vs Temperature
INA226 tc_histo_bus_input_offset_v_distrib_bos547.gif
Figure 8. Bus Input Offset Voltage Production Distribution
INA226 tc_histo_bus_input_gain_err_distrib_bos547.gif
Figure 10. Bus Input Gain Error Production Distribution
INA226 g015_bos547.png
Figure 12. Input Bias Current vs Common-Mode Voltage
INA226 g017_bos547.png
Figure 14. Input Bias Current vs Temperature, Shutdown
INA226 g019_bos547.png
Figure 16. Shutdown IQ vs Temperature
INA226 tc_shutdown_iq_i2c_fqcy_bos547.gif
Figure 18. Shutdown IQ vs I2C Clock Frequency