SBOS770A May   2017  – June 2017 INA826S

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inside the INA826S
      2. 7.3.2 Setting the Gain
        1. 7.3.2.1 Gain Drift
      3. 7.3.3 Offset Trimming
      4. 7.3.4 Input Common-Mode Range
      5. 7.3.5 Input Protection
      6. 7.3.6 Input Bias Current Return Path
      7. 7.3.7 Reference Pin (REF)
      8. 7.3.8 Shutdown (EN and ENREF) Pins
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Low-Voltage Operation
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications. The bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry, because noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp specifically.
  • Connect the device reference pin to a low-impedance, low-noise, system reference point, such as an analog ground. If a potential other than ground is used as a reference, a low output impedance (such as a voltage divider with an op amp buffer) must be included.
  • Minimize the parasitic capacitance and inductance present at the gain resistor connections. Place the gain resistor as close to the device as possible, and remove the ground plane around the gain resistor to minimize parasitic capacitances at these nodes.
  • For best performance, route the input traces adjacent to each other as a differential pair.
  • For proper amplifier function, connect the package thermal pad to the most negative supply voltage (VEE).

10.2 Layout Example

INA826S ai_D002_SBOS770.gif Figure 77. INA826S PCB Layout Example