SLLSEY2E March 2017  – November 2017 ISOW7840 , ISOW7841 , ISOW7842 , ISOW7843 , ISOW7844

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Ratings
    6. 7.6 Insulation Specifications
    7. 7.7 Safety-Related Certifications
    8. 7.8 Safety Limiting Values
    9. 7.9 Electrical Characteristics—5-V Input, 5-V Output
    10. 7.10Supply Current Characteristics—5-V Input, 5-V Output
    11. 7.11Electrical Characteristics—5-V Input, 3.3-V Output
    12. 7.12Supply Current Characteristics—5-V Input, 3.3-V Output
    13. 7.13Electrical Characteristics—3.3-V Input, 3.3-V Output
    14. 7.14Supply Current Characteristics—3.3-V Input, 3.3-V Output
    15. 7.15Switching Characteristics—5-V Input, 5-V Output
    16. 7.16Switching Characteristics—5-V Input, 3.3-V Output
    17. 7.17Switching Characteristics—3.3-V Input, 3.3-V Output
    18. 7.18Insulation Characteristics Curves
    19. 7.19Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2Power-Up and Power-Down Behavior
      3. 9.3.3Current Limit, Thermal Overload Protection
    4. 9.4Device Functional Modes
      1. 9.4.1Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
      3. 10.2.3Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
      1. 12.1.1PCB Material
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Device Support
      1. 13.1.1Development Support
    2. 13.2Documentation Support
      1. 13.2.1Related Documentation
    3. 13.3Related Links
    4. 13.4Receiving Notification of Documentation Updates
    5. 13.5Community Resources
    6. 13.6Trademarks
    7. 13.7Electrostatic Discharge Caution
    8. 13.8Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DWE|16
Orderable Information

Detailed Description

Overview

The ISOW784x family of devices comprises a high-efficiency, low-emissions isolated DC-DC converter and four high-speed isolated data channels. Figure 34 shows the functional block diagram of the ISOW784x family of devices.

The integrated DC-DC converter uses switched mode operation and proprietary circuit techniques to reduce power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of a high-Q on-chip transformer provide high efficiency and low radiated emissions. The integrated transformer uses thin film polymer as the insulation barrier.

The VCC supply is provided to the primary power controller that switches the power stage connected to the integrated transformer. Power is transferred to the secondary side, rectified and regulated to either 3.3 V or 5 V, depending on the SEL pin. The output voltage, VISO, is monitored and feedback information is conveyed to the primary side through a dedicated isolation channel. The duty cycle of the primary switching stage is adjusted accordingly. The fast feedback control loop of the power converter ensures low overshoots and undershoots during load transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VCC and VISO supplies which ensures robust system performance under noisy conditions. An integrated soft-start mechanism ensures controlled inrush current and avoids any overshoot on the output during power up.

The integrated signal-isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across the barrier to represent one state and sends no signal to represent the other state. The receiver demodulates the signal after signal conditioning and produces the output through a buffer stage. The signal-isolation channels incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions from the high frequency carrier and IO buffer switching. Figure 35 shows a functional block diagram of a typical signal isolation channel.

The ISOW784x family of devices is suitable for applications that have limited board space and require more integration. These devices are also suitable for very-high voltage applications, where power transformers meeting the required isolation specifications are bulky and expensive.

Functional Block Diagram

ISOW7840 ISOW7841 ISOW7842 ISOW7843 ISOW7844 isow784x-block-diagram.gif Figure 34. ISOW784x Block Diagram
ISOW7840 ISOW7841 ISOW7842 ISOW7843 ISOW7844 fbd_sllsep3.gif Figure 35. Conceptual Block Diagram of a Capacitive Data Channel

Figure 36 shows a conceptual detail of how the OOK scheme works.

ISOW7840 ISOW7841 ISOW7842 ISOW7843 ISOW7844 on_off_keying_sllsem2.gif Figure 36. On-Off Keying (OOK) Based Modulation Scheme

Feature Description

Table 1 provides an overview of the device features.

Table 1. Device Features

PART NUMBER(1)CHANNEL DIRECTIONMAXIMUM DATA RATEDEFAULT OUTPUT STATERATED ISOLATION(2)
ISOW78404 forward, 0 reverse100 MbpsHigh5 kVRMS / 7071 VPK
ISOW7840FLow
ISOW78413 forward, 1 reverseHigh
ISOW7841FLow
ISOW78422 forward, 2 reverseHigh
ISOW7842FLow
ISOW78431 forward, 3 reverseHigh
ISOW7843FLow
ISOW78440 forward, 4 reverseHigh
ISOW7844FLow
The F suffix is part of the orderable part number. See the Mechanical, Packaging, and Orderable Information section for the full orderable part number.
For detailed isolation ratings, see the Safety-Related Certifications table.

Electromagnetic Compatibility (EMC) Considerations

The ISOW784x family of devices use emissions reduction schemes for the internal oscillator and advanced internal layout scheme to minimize radiated emissions at the system level.

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISOW784x family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include:

  • Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
  • Low-resistance connectivity of ESD cells to supply and ground pins.
  • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
  • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
  • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
  • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

Power-Up and Power-Down Behavior

The ISOW784x family of devices has built-in UVLO on the VCC and VISO supplies with positive-going and negative-going thresholds and hysteresis. When the VCC voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits primary peak currents drawn from the VCC supply and charges the VISO output in a controlled manner, avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VCC or VISO voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the secondary side VISO pin, the feedback data channel starts providing feedback to the primary controller. The regulation loop takes over and the isolated data channels go to the normal state defined by the respective input channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.

When VCC power is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached. The VISO capacitor then discharges depending on the external load. The isolated data outputs on the VISO side are returned to the default state for the brief time that the VISO voltage takes to discharge to zero.

Current Limit, Thermal Overload Protection

The ISOW784x family of devices is protected against output overload and short circuit. Output voltage starts dropping when the power converter is not able to deliver the current demanded during overload conditions. For a VISO short-circuit to ground, the duty cycle of the converter is limited to help protect against any damage.

Thermal protection is also integrated to help prevent the device from getting damaged during overload and short-circuit conditions on the isolated output. Under these conditions, the device temperature starts to increase. When the temperature goes above 180°C, thermal shutdown activates and the primary controller turns off which removes the energy supplied to the VISO load, which causes the device to cool off. When the junction temperature goes below 150°C, the device starts to function normally. If an overload or output short-circuit condition prevails, this protection cycle is repeated. Care should be taken in the design to prevent the device junction temperatures from reaching such high values.

Device Functional Modes

Table 2 lists the supply configurations for these devices.

Table 2. Supply Configurations

SEL INPUTVCCVISO
Shorted to VISO5 V5 V
Shorted to GND2 or floating5 V3.3 V
Shorted to GND2 or floating3.3 V(1)3.3 V(2)
VCC = 3.3 V, SEL shorted to VISO (essentially VISO = 5 V) is not recommended mode of configuration.
The SEL pin has a weak pulldown internally. Therefore for VISO = 3.3 V, the SEL pin should be strongly connected to the GND2 pin in noisy system scenarios.

Table 3 lists the functional modes for ISOW784x devices.

Table 3. Function Table(1)

INPUT SUPPLY
(VCC)
INPUT
(INx)
OUTPUT
(OUTx)
COMMENTS
PUHHOutput channel assumes the logic state of its input
LL
OpenDefaultDefault mode(2): When INx is open, the corresponding output channel assumes logic based on default output mode of selected version
PDxUndetermined(3)
PU = Powered up (VCC ≥ 2.7 V); PD = Powered down (VCC < 2.1 V); X = Irrelevant; H = High level; L = Low level, VCC = Input-side supply
In the default condition, the output is high for ISOW784x and low for ISOW784x with the F suffix.
The outputs are in an undetermined state when VCC < 2.1 V.

Device I/O Schematics

ISOW7840 ISOW7841 ISOW7842 ISOW7843 ISOW7844 isow784x-device-io-schematics.gif Figure 37. Device I/O Schematics