SLLSEY2E March 2017  – November 2017 ISOW7840 , ISOW7841 , ISOW7842 , ISOW7843 , ISOW7844


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Ratings
    6. 7.6 Insulation Specifications
    7. 7.7 Safety-Related Certifications
    8. 7.8 Safety Limiting Values
    9. 7.9 Electrical Characteristics—5-V Input, 5-V Output
    10. 7.10Supply Current Characteristics—5-V Input, 5-V Output
    11. 7.11Electrical Characteristics—5-V Input, 3.3-V Output
    12. 7.12Supply Current Characteristics—5-V Input, 3.3-V Output
    13. 7.13Electrical Characteristics—3.3-V Input, 3.3-V Output
    14. 7.14Supply Current Characteristics—3.3-V Input, 3.3-V Output
    15. 7.15Switching Characteristics—5-V Input, 5-V Output
    16. 7.16Switching Characteristics—5-V Input, 3.3-V Output
    17. 7.17Switching Characteristics—3.3-V Input, 3.3-V Output
    18. 7.18Insulation Characteristics Curves
    19. 7.19Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2Power-Up and Power-Down Behavior
      3. 9.3.3Current Limit, Thermal Overload Protection
    4. 9.4Device Functional Modes
      1. 9.4.1Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
      3. 10.2.3Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
      1. 12.1.1PCB Material
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Device Support
      1. 13.1.1Development Support
    2. 13.2Documentation Support
      1. 13.2.1Related Documentation
    3. 13.3Related Links
    4. 13.4Receiving Notification of Documentation Updates
    5. 13.5Community Resources
    6. 13.6Trademarks
    7. 13.7Electrostatic Discharge Caution
    8. 13.8Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DWE|16
Orderable Information


Layout Guidelines

A minimum of four layers is required to accomplish a low-EMI PCB design (see Figure 41). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane, and low-frequency signal layer.

  • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
  • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
  • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2.
  • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
  • Keep decoupling capacitors as close as possible to the VCC and VISO pins.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective GND pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature of the device from rising to unacceptable levels.

The ISOW784x integrated signal and power isolation device simplifies system design and reduces board area. The use of low-inductance micro-transformers in the ISOW784x device necessitates the use of high frequency switching, resulting in higher radiated emissions compared to discrete solutions. The ISOW784x device uses on-chip circuit techniques to reduce emissions compared to competing solutions. For further reduction in radiated emissions at system level, refer to the Low-Emission Designs With ISOW7841 Integrated Signal and Power Isolator application report.

PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics.

Layout Example

ISOW7840 ISOW7841 ISOW7842 ISOW7843 ISOW7844 isow784x-layout-example.gif Figure 41. Layout Example