Product details

Number of channels 1 Rail-to-rail No GBW (typ) (MHz) 5 Slew rate (typ) (V/µs) 12 Vos (offset voltage at 25°C) (max) (mV) 5 Iq per channel (typ) (mA) 5 Vn at 1 kHz (typ) (nV√Hz) 12 Rating Military Operating temperature range (°C) -55 to 125 Offset drift (typ) (µV/°C) 5 Input bias current (max) (pA) 100 CMRR (typ) (dB) 100 Iout (typ) (A) 0.025 Architecture FET Input common mode headroom (to negative supply) (typ) (V) 3 Input common mode headroom (to positive supply) (typ) (V) 0.1 Output swing headroom (to negative supply) (typ) (V) 2 Output swing headroom (to positive supply) (typ) (V) -2
Number of channels 1 Rail-to-rail No GBW (typ) (MHz) 5 Slew rate (typ) (V/µs) 12 Vos (offset voltage at 25°C) (max) (mV) 5 Iq per channel (typ) (mA) 5 Vn at 1 kHz (typ) (nV√Hz) 12 Rating Military Operating temperature range (°C) -55 to 125 Offset drift (typ) (µV/°C) 5 Input bias current (max) (pA) 100 CMRR (typ) (dB) 100 Iout (typ) (A) 0.025 Architecture FET Input common mode headroom (to negative supply) (typ) (V) 3 Input common mode headroom (to positive supply) (typ) (V) 0.1 Output swing headroom (to negative supply) (typ) (V) 2 Output swing headroom (to positive supply) (typ) (V) -2
TO-CAN (LMC) 8 80.2816 mm² 8.96 x 8.96
  • Advantages
    • Replace Expensive Hybrid and Module FET Op Amps
    • Rugged JFETs Allow Blow-Out Free Handling Compared with MOSFET Input Devices
    • Excellent for Low Noise Applications using either High or Low Source Impedance—Very Low 1/f Corner
    • Offset Adjust does not Degrade Drift or Common-Mode Rejection as in Most Monolithic Amplifiers
    • New Output Stage Allows use of Large Capacitive Loads (5,000 pF) without Stability Problems
    • Internal Compensation and Large Differential Input Voltage Capability

Common Features

  • Low Input Bias Current: 30pA
  • Low Input Offset Current: 3pA
  • High Input Impedance: 1012Ω
  • Low Input Noise Current: 0.01 pA / √Hz
  • High Common-Mode Rejection Ratio: 100 dB
  • Large DC Voltage Gain: 106 dB

Uncommon Features

  • Extremely Fast Settling Time to 0.01% 1.5μs
  • Fast Slew Rate 12V/µs
  • Wide Gain Bandwidth 5MHz
  • Low Input Noise Voltage 12 nV / √Hz

All trademarks are the property of their respective owners.

  • Advantages
    • Replace Expensive Hybrid and Module FET Op Amps
    • Rugged JFETs Allow Blow-Out Free Handling Compared with MOSFET Input Devices
    • Excellent for Low Noise Applications using either High or Low Source Impedance—Very Low 1/f Corner
    • Offset Adjust does not Degrade Drift or Common-Mode Rejection as in Most Monolithic Amplifiers
    • New Output Stage Allows use of Large Capacitive Loads (5,000 pF) without Stability Problems
    • Internal Compensation and Large Differential Input Voltage Capability

Common Features

  • Low Input Bias Current: 30pA
  • Low Input Offset Current: 3pA
  • High Input Impedance: 1012Ω
  • Low Input Noise Current: 0.01 pA / √Hz
  • High Common-Mode Rejection Ratio: 100 dB
  • Large DC Voltage Gain: 106 dB

Uncommon Features

  • Extremely Fast Settling Time to 0.01% 1.5μs
  • Fast Slew Rate 12V/µs
  • Wide Gain Bandwidth 5MHz
  • Low Input Noise Voltage 12 nV / √Hz

All trademarks are the property of their respective owners.

This is the first monolithic JFET input operational amplifier to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). This amplifier features low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The device is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/ƒ noise corner.

This is the first monolithic JFET input operational amplifier to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). This amplifier features low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The device is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/ƒ noise corner.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet LF156JAN JFET Input Operational Amplifiers datasheet (Rev. A) 25 Mar 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Calculation tool

ANALOG-ENGINEER-CALC — Analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
Design tool

CIRCUIT060013 — Inverting amplifier with T-network feedback circuit

This design inverts the input signal, VIN, and applies a signal gain of 1000 V/V or 60 dB. The inverting amplifier with T-feedback network can be used to obtain a high gain without a small value for R4 or very large values for the feedback resistors.
Design tool

CIRCUIT060015 — Adjustable reference voltage circuit

This circuit combines an inverting and non-inverting amplifier to make a reference voltage adjustable from the negative of the input voltage up to the input voltage. Gain can be added to increase the maximum negative reference level.
Design tool

CIRCUIT060074 — High-side current sensing with comparator circuit

This high-side, current sensing solution uses one comparator with a rail-to-rail input common mode range to create an over-current alert (OC-Alert) signal at the comparator output (COMP OUT) if the load current rises above 1 A. The OC-Alert signal in this implementation is active low. So when the (...)
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins Download
TO-CAN (LMC) 8 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos