SNVS483H January   2007  – August 2017 LM25574

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Voltage Start-Up Regulator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown and Stand-by Mode
      2. 7.4.2 Oscillator and Sync Capability
      3. 7.4.3 Error Amplifier and PWM Comparator
      4. 7.4.4 Ramp Generator
      5. 7.4.5 Maximum Duty Cycle and Input Drop-out Voltage
      6. 7.4.6 Current Limit
      7. 7.4.7 Soft-Start
      8. 7.4.8 Boost Pin
      9. 7.4.9 Thermal Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  External Components
      2. 8.1.2  R3 (RT)
      3. 8.1.3  L1
      4. 8.1.4  C3 (CRAMP)
      5. 8.1.5  C9
      6. 8.1.6  C1
      7. 8.1.7  C8
      8. 8.1.8  C7
      9. 8.1.9  C4
      10. 8.1.10 R5, R6
      11. 8.1.11 R1, R2, C2
      12. 8.1.12 R4, C5, C6
      13. 8.1.13 Bias Power Dissipation Reduction
    2. 8.2 Typical Application
      1. 8.2.1 Typical Schematic for High Frequency (1MHz) Application
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PCB Layout and Thermal Considerations
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Developmental Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.12 R4, C5, C6

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM25574 is as follows:

Equation 13. DC Gain(MOD) = Gm(MOD) x RLOAD = 0.5 x RLOAD

The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD,) and output capacitance (COUT). The corner frequency of this pole is:

Equation 14. fp(MOD) = 1 / (2π RLOAD COUT)

For RLOAD = 20Ω and COUT = 22µF then fp(MOD) = 362Hz

DC Gain(MOD) = 0.5 x 20 = 20dB

For the design example of Functional Block Diagram the following modulator gain vs. frequency characteristic was measured as shown in Figure 15.

LM25574 20214115.gifFigure 15. Gain and Phase of Modulator RLOAD = 20 Ohms and COUT = 22µF

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a zero at fZ = 1 / (2πR4C5). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 25kHz was selected. The compensation network zero (fZ) should be selected at least an order of magnitude less than the target crossover frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4 C5) to be less than 2 kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was selected for 0.022 µF and R4 was selected for 24.9 kΩ. These values configure the compensation network zero at 290 Hz. The error amp gain at frequencies greater than fZ is: R4 / R5, which is approximately 5 (14dB).

LM25574 20214116.gifFigure 16. Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

LM25574 20214117.gifFigure 17. Overall Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response. C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of C6 must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by C6 is: fp2 = fz x C5 / C6.