LMC6482

(ACTIVE) Ultra-low Bias Current, Precision CMOS Rail-to-Rail Input and Output Operational Amplifier

Diagrams

Functional diagram

Typical Performance

Description

The LMC6482 device provides a common-mode range that extends to both supply rails. This rail-to-rail performance combined with excellent accuracy, due to a high CMRR, makes it unique among rail-to-rail input amplifiers. The device is ideal for systems, such as data acquisition, that require a large input signal range. The LMC6482 is also an excellent upgrade for circuits using limited common-mode range amplifiers such as the TLC272 and TLC277.

Maximum dynamic signal range is assured in low voltage and single supply systems by the rail-to-rail output swing of the LMC6482. The rail-to-rail output swing is ensured for loads down to 600 Ω of the device. Ensured low-voltage characteristics and low-power dissipation make the LMC6482 especially well-suited for battery-operated systems. LMC6482 is also available in a VSSOP package, which is almost half the size of a SOIC-8 device. See the LMC6484 data sheet for a quad CMOS operational amplifier with these same features.

Features

  • Typical Unless Otherwise Noted
  • Rail-to-Rail Input Common-Mode Voltage Range
    (Ensured Over Temperature)
  • Rail-to-Rail Output Swing (Within 20-mV of Supply
    Rail, 100-kΩ Load)
  • Ensured 3-V, 5-V, and 15-V Performance
  • Excellent CMRR and PSRR: 82 dB
  • Ultralow Input Current: 20 fA
  • High Voltage Gain (R L = 500 k Ω): 130 dB
  • Specified for 2-kΩ and 600-Ω Loads
  • Power-Good Output
  • Available in VSSOP Package

Parametrics

Number of Channels (#) 2   
Total Supply Voltage (Min) (+5V=5, +/-5V=10) 3   
Total Supply Voltage (Max) (+5V=5, +/-5V=10) 15.5   
GBW (Typ) (MHz) 1.5   
Slew Rate (Typ) (V/us) 1.3   
Rail-to-Rail In^Out   
Vos (Offset Voltage @ 25C) (Max) (mV) 0.75   
Offset Drift (Typ) (uV/C) 1   
Iq per channel (Typ) (mA) 0.5   
Vn at 1kHz (Typ) (nV/rtHz) 37   
CMRR (Typ) (dB) 82   
Operating Temperature Range (C) -40 to 85   
Package Group PDIP^SOIC^VSSOP   
Package Size: mm2:W x L (PKG) See datasheet (PDIP)^8SOIC: 29 mm2: 6 x 4.9(SOIC)^8VSSOP: 15 mm2: 4.9 x 3(VSSOP)   
Input Bias Current (Max) (pA) 4   
Output Current (Typ) (mA) 30   
Features N/A   
Architecture CMOS   

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Technical Documents

Datasheet (1)

Application notes (4)

More literature (1)

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