SBOS709A July 2016  – July 2016 LMH2832

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6Timing Requirements: SPI
    7. 7.7Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1Setup Diagrams
    2. 8.2ATE Testing and DC Measurements
    3. 8.3Frequency Response
    4. 8.4Distortion
    5. 8.5Noise Figure
    6. 8.6Pulse Response, Slew Rate, and Overdrive Recovery
    7. 8.7Power-Down
    8. 8.8Crosstalk, Gain Matching, and Phase Matching
    9. 8.9Output Measurement Reference Points
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1Analog Input Characteristics
      2. 9.3.2Analog Output Characteristics
      3. 9.3.3Driving Low Insertion-Loss Filters
      4. 9.3.4Input Impedance Matching
      5. 9.3.5Power-On Reset (POR)
    4. 9.4Device Functional Modes
      1. 9.4.1Power-Down (PD)
      2. 9.4.2Gain Control
    5. 9.5Programming
      1. 9.5.1Details of the Serial Interface
      2. 9.5.2Timing Diagrams
    6. 9.6Register Maps
      1. 9.6.1Register Descriptions
        1. 9.6.1.1SW Reset Register (address = 2)
      2. 9.6.2Power-Down Control Register (address = 3)
      3. 9.6.3Channel A RW0 Register (address = 4)
      4. 9.6.4Channel A RW1 Register (address = 5)
      5. 9.6.5Channel B RW0 Register (address = 6)
      6. 9.6.6Channel B RW1 Register (address = 7)
  10. 10Application and Implementation
    1. 10.1Application Information
      1. 10.1.1Driving ADCs
        1. 10.1.1.1SNR Considerations
        2. 10.1.1.2SFDR Considerations
        3. 10.1.1.3ADC Input Common-Mode Voltage Considerations (AC-Coupled Input)
        4. 10.1.1.4ADC Input Common-Mode Voltage Considerations (DC-Coupled Input)
    2. 10.2Typical Applications
      1. 10.2.1DOCSIS 3.X Driver
        1. 10.2.1.1Design Requirements
        2. 10.2.1.2Detailed Design Procedure
          1. 10.2.1.2.1Source Resistance Matching
          2. 10.2.1.2.2Output Impedance Matching
          3. 10.2.1.2.3Voltage Headroom Considerations
        3. 10.2.1.3Application Curve
      2. 10.2.2IQ Receiver
    3. 10.3Do's and Don'ts
      1. 10.3.1Do:
      2. 10.3.2Don't:
  11. 11Power Supply Recommendations
    1. 11.1Split Supplies
    2. 11.2Supply Decoupling
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Device Support
      1. 13.1.1Device Nomenclature
    2. 13.2Documentation Support
      1. 13.2.1Related Documentation
    3. 13.3Receiving Notification of Documentation Updates
    4. 13.4Community Resources
    5. 13.5Trademarks
    6. 13.6Electrostatic Discharge Caution
    7. 13.7Glossary
  14. 14Mechanical, Packaging, and Orderable Information

1 Features

  • Dual-Channel, Individual SPI™-Controlled DVGA
  • Single 5-V Supply
  • –3-dB Bandwidth: 1.1 GHz (Max Gain)
  • Flat Bandwidth Response: 300 MHz
  • Channel-to-Channel Gain Matching: ±0.05 dB
  • Channel-to-Channel Phase Matching: ±0.1°
  • Gain:
    • 30 dB to –9 dB
    • 1-dB Steps ±0.2 dB
  • Output Third-Order Intercept Point (OIP3):
    • 43 dBm at 300 MHz
    • 51 dBm at 200 MHz
  • Noise Figure (NF):
    • 6.5 dB (Max Gain) at 300 MHz, ZIN = 150 Ω
  • Adjustable Power Consumption:
    • 90 mA to 108 mA per Channel
  • Power-Saving, Power-Down Feature:
    • IQ < 4.5 mA per Channel
    • Power-Down Pin and SPI Programmability
  • Input Return Loss at 300 MHz:
    • 17 dB (RS = 150 Ω)

2 Applications

  • DOCSIS 3.1 CMTS Upstream Direct Sampling Receivers
  • CATV Modem Signal Scaling
  • Programmable Gain IF Amplifiers
  • Generic RF, IF Gain Stages
  • ADC Drivers

3 Description

The LMH2832 is a high-linearity, dual-channel, digital variable-gain amplifier (DVGA) for high-speed signal chain and data-acquisition systems. The LMH2832 is optimized to provide high bandwidth, low distortion, and low noise, thus making the device ideally suited as a dual, 14-bit, analog-to-digital converter (ADC) driver. The device consists of one fixed-gain block and one variable attenuator consisting of a total gain of 30 dB with a maximum attenuation of 39 dB. The gain range is from 30 dB to –9 dB in 1-dB gain steps with a gain accuracy of ±0.2 dB. The input impedance can be easily matched to 50-Ω or 75-Ω systems using a 1:3-Ω or 1:2-Ω ratio balun, respectively. The LMH2832 is designed to drive general-purpose ADCs and also meets the requirements for both data over cable service interface specification (DOCSIS) 3.0 32 quadrature amplitude modulation (QAM) carriers and DOCSIS 3.1 wideband orthogonal frequency-division multiplexing (OFDM) systems. With excellent NF (6.5 dB) and linearity, the LMH2832 is designed to perform to within DOCSIS specifications. The quiescent current in the power-down state is less than 5 mA per channel with the typical current consumption during operation at 105 mA per channel.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
LMH2832VQFN (40)6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Output Third-Order Intercept Point (OIP3) Performance

LMH2832 D005_SBOS709.gif