SBOS730A April 2015  – May 2015 LMH6401


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6SPI Timing Requirements
    7. 7.7Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1Setup Diagrams
    2. 8.2Output Measurement Reference Points
    3. 8.3ATE Testing and DC Measurements
    4. 8.4Frequency Response
    5. 8.5Distortion
    6. 8.6Noise Figure
    7. 8.7Pulse Response, Slew Rate, and Overdrive Recovery
    8. 8.8Power Down
    9. 8.9VOCM Frequency Response
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
    4. 9.4Device Functional Modes
      1. 9.4.1Power-On Reset (POR)
      2. 9.4.2Power-Down (PD)
      3. 9.4.3Thermal Feedback Control
      4. 9.4.4Gain Control
    5. 9.5Programming
      1. 9.5.1Details of the Serial Interface
      2. 9.5.2Timing Diagrams
    6. 9.6Register Maps
      1. 9.6.1Revision ID (address = 0h, Read-Only) [default = 03h]
      2. 9.6.2Product ID (address = 1h, Read-Only) [default = 00h]
      3. 9.6.3Gain Control (address = 2h) [default = 20h]
      4. 9.6.4Reserved (address = 3h) [default = 8Ch]
      5. 9.6.5Thermal Feedback Gain Control (address = 4h) [default = 27h]
      6. 9.6.6Thermal Feedback Frequency Control (address = 5h) [default = 45h]
  10. 10Application and Implementation
    1. 10.1Application Information
      1. 10.1.1Analog Input Characteristics
      2. 10.1.2 Analog Output Characteristics
        1. Capacitive Loads
      3. 10.1.3Thermal Feedback Control
        1. Response Optimization using Thermal Feedback Control
      4. 10.1.4Thermal Considerations
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
        1. ADCs
          1. Considerations
          2. Considerations
          3. Input Common-Mode Voltage Considerations—AC-Coupled Input
          4. Input Common-Mode Voltage Considerations—DC-Coupled Input
      3. 10.2.3Application Curves
    3. 10.3Do's and Don'ts
      1. 10.3.1Do:
      2. 10.3.2Don't:
  11. 11Power-Supply Recommendations
    1. 11.1Single-Supply Operation
    2. 11.2Split-Supply Operation
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Examples
  13. 13Device and Documentation Support
    1. 13.1Documentation Support
      1. 13.1.1Related Documentation
    2. 13.2Community Resources
    3. 13.3Trademarks
    4. 13.4Electrostatic Discharge Caution
    5. 13.5Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9 Detailed Description

9.1 Overview

The LMH6401 is a very high-performance, differential I/O, digitally-controlled variable gain amplifier (DVGA). The device is optimized for radio frequency (RF), intermediate frequency (IF), or high-speed time-domain applications with 3-dB bandwidths up to 4.5 GHz. The device is ideal for dc- or ac-coupled applications requiring a variable gain stage when driving an analog-to-digital converter (ADC).

The LMH6401 is best suited to optimize system linearity and noise performance over the entire gain range in the RF and IF bands. Operating on a nominal 5-V supply or ±2.5-V split supplies, the device consists of an attenuator stage followed by a fixed-gain amplifier to provide voltage gain control from –6 dB to 26 dB in 1-dB steps (as shown in the Functional Block Diagram section) with an overall 32-dB gain range. The variable gain control for the device is offered through the digital serial peripheral interface (SPI) register. The device has a unique attenuator ladder architecture providing dynamic range improvements where the overall noise figure (NF) remains relatively constant for the first 5-dB attenuator steps, with NF degrading proportional to the attenuator steps on the sixth step. This behavior repeats over the entire gain range; see Figure 26.

The device has a differential input impedance of 100-Ω and is intended to be driven differentially by a matched 100-Ω differential source impedance for the best linearity and noise performance. The LMH6401 has two on-chip, 10-Ω resistors, one on each output (as shown in the Functional Block Diagram section). For most load conditions, the 10-Ω resistors are only a partial termination. Consequently, external termination resistors are required in most applications. See Table 11 for common load values and the matching resistors.

The LMH6401 supports a common-mode reference input (VOCM) pin to align the amplifier output common-mode with the subsequent stage (ADC) input requirements. The output common-mode of the LMH6401 is self-biased to mid-supply when the VOCM pin is not driven externally. The device can be operated on a power-supply voltage range of 4.0 V to 5.25 V and supports both single- and split-supply operation. For correct digital operation, the positive supply must not be below 2 V for ground reference logic. A power-down feature is also available through the SPI register and the external PD pin.

9.2 Functional Block Diagram

LMH6401 FunctionalBD_01_SBOS730.gif

9.3 Feature Description

The LMH6401 includes the following features:

  • Fully-differential amplifier
  • Digitally-controlled variable gain: –6 dB to 26 dB in 1-dB steps
  • Output common-mode control
  • Single- or split-supply operation
  • Large-signal bandwidth of 4.5 GHz
  • Usable bandwidth up to 2 GHz
  • Power-down control

9.4 Device Functional Modes

9.4.1 Power-On Reset (POR)

The LMH6401 has a built-in, power-on reset (POR) that sets the device registers to their default state (see Table 3) on power-up. Note that the LMH6401 register information is lost each time power is removed. When power is reapplied, the POR ensures the device enters a default state. Power glitches (of sufficient duration) can also initiate the POR and return the device to a default state.

9.4.2 Power-Down (PD)

The device supports power-down control using an external power-down (PD) pin or by writing a logic high to bit 6 of SPI register 2h (see the Register Maps section). The external PD is an active high pin. When left floating, the device defaults to an on condition when the PD pin defaults to logic low as a result of the internal pulldown resistor. The device PD thresholds are noted in the Electrical Characteristics table. The device consumes approximately 7 mA in power-down mode. Note that the SPI register contents are preserved in power-down mode.

9.4.3 Thermal Feedback Control

The LMH6401 has a thermal feedback gain and frequency control feature that allows for improved low-frequency settling performance. The Thermal Feedback Gain Control and Thermal Feedback Frequency Control registers set through the SPI control this feature. The default setting is described in Table 3. Graphs are Included in the Application and Implementation section that illustrate how the thermal feedback gain and frequency control allows for enhanced performance.

9.4.4 Gain Control

The LMH6401 gain can be controlled from 26-dB gain (0-dB attenuation) to –6-dB gain in 1-dB steps by digitally programming the SPI register 2h. See the Register Maps section for more details.

9.5 Programming

9.5.1 Details of the Serial Interface

The LMH6401 has a set of internal registers that can be accessed by the serial interface controlled by the CS (chip select), SCLK (serial interface clock), SDI (serial interface input data), and SDO (serial interface readback data) pins. Serial input to the device is enabled when CS is low. SDI serial data are latched at every SCLK rising edge when CS is active (low). Serial data are loaded into the register at every 16th SCLK rising edge when CS is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active CS pulse. The first eight bits form the register address and the remaining eight bits form the register data. The interface can function with SCLK frequencies from 50 MHz down to very low speeds (of a few Hertz) and also with a non-50% SCLK duty cycle. A summary of the LMH6401 SPI protocol follows:

  • SPI-1.1 compliant interface
  • SPI register contents protected in power-down
  • SPI-controlled power-down
  • Powered from the main VS+ power supply
  • 1.8-V logic compliant

9.5.2 Timing Diagrams

Figure 47 and Figure 48 show timing diagrams for the SPI write and read bus cycles, respectively. Figure 49 and Figure 50 show timing diagrams for the write and read operations, respectively, of the LMH6401. Figure 51 and Figure 52 illustrate example SPI stream write and read timing diagrams, respectively. Refer to the Electrical Characteristics table for SPI timing requirements.

LMH6401 pmi_spi_wr_bus_tim_sbos730.gifFigure 47. SPI Write Bus Cycle
LMH6401 pmi_spi_rd_bus_tim_sbos730.gifFigure 48. SPI Read Bus Cycle
LMH6401 WriteTiming_01_SBOS730.gifFigure 49. Write Operation Timing Diagram
LMH6401 ReadTiming_01_SBOS730.gifFigure 50. Read Operation Timing Diagram
LMH6401 pmi_spi_stream_wr_tim_sbos730.gifFigure 51. SPI Streaming Write Example
LMH6401 pmi_spi_stream_rd_tim_sbos730.gifFigure 52. SPI Streaming Read Example

9.6 Register Maps

Table 3 lists the SPI register map.

Table 3. SPI Register Map

0RRevision ID03h
1RProduct ID00h
2R/WGain Control20h (minimum gain)
4R/WThermal feedback gain control 27h
5R/WThermal feedback frequency control45h

9.6.1 Revision ID (address = 0h, Read-Only) [default = 03h]

Figure 53. Revision ID
Revision ID
LEGEND: R = Read only; -n = value after reset

Table 4. Revision ID Field Descriptions

7-0Revision IDR00000011Revision identification bits.

9.6.2 Product ID (address = 1h, Read-Only) [default = 00h]

Figure 54. Product ID
Product ID
LEGEND: R = Read only; -n = value after reset

Table 5. Product ID Field Descriptions

7-0Product IDR00000000Product identification bits.

9.6.3 Gain Control (address = 2h) [default = 20h]

Figure 55. Gain Control
ReservedPower DownGain Control
LEGEND: R/W = Read/Write; -n = value after reset

Table 6. Gain Control Field Description

7ReservedR/W0Reserved, always program to 0
6Power DownR/W00 = Active
1 = Power down
5-0Gain ControlR/W100000Gain control (see Table 10 for gain settings)

9.6.4 Reserved (address = 3h) [default = 8Ch]

Figure 56. Reserved
LEGEND: R/W = Read/Write; -n = value after reset

Table 7. Reserved Field Descriptions


9.6.5 Thermal Feedback Gain Control (address = 4h) [default = 27h]

Figure 57. Thermal Feedback Gain Control
ReservedReservedThermal SDThermal Feedback Gain Control
LEGEND: R/W = Read/Write; -n = value after reset

Table 8. Thermal Feedback Gain Control Field Descriptions

7-6ReservedR/W00Reserved, always program to 00
5Thermal SDR/W10 = Thermal feedback control enabled
1 = Thermal feedback control disabled
4-0Thermal Feedback Gain ControlR/W0011100000 = Minimum thermal feedback gain (see Figure 61)
11111 = Maximum thermal feedback gain (see Figure 61)

9.6.6 Thermal Feedback Frequency Control (address = 5h) [default = 45h]

Figure 58. Thermal Feedback Frequency Control
ReservedReservedReservedThermal Feedback Frequency Control
LEGEND: R/W = Read/Write; -n = value after reset

Table 9. Thermal Feedback Frequency Control Field Descriptions

7-5ReservedR/W010Reserved, always program to 010
4-0Thermal Feedback Frequency ControlR/W0010100000 = Minimum thermal feedback frequency (see Figure 62)
11111 = Maximum thermal feedback frequency (see Figure 62)

Table 10. Gain Control Register Controls

125 01h
224 02h
323 03h
422 04h
521 05h
620 06h
719 07h
818 08h
917 09h
1016 0Ah
1115 0Bh
1214 0Ch
1313 0Dh
1412 0Eh
1511 0Fh
1610 10h
179 11h
188 12h
197 13h
206 14h
215 15h
224 16h
233 17h
242 18h
251 19h
260 1Ah
27–1 1Bh
28–2 1Ch
29–3 1Dh
30–4 1Eh
31–5 1Fh
32–6 20h-3Fh