The LMH6401 is a very high-performance, differential I/O, digitally-controlled variable gain amplifier (DVGA). The device is optimized for radio frequency (RF), intermediate frequency (IF), or high-speed time-domain applications with 3-dB bandwidths up to 4.5 GHz. The device is ideal for dc- or ac-coupled applications requiring a variable gain stage when driving an analog-to-digital converter (ADC).
The LMH6401 is best suited to optimize system linearity and noise performance over the entire gain range in the RF and IF bands. Operating on a nominal 5-V supply or ±2.5-V split supplies, the device consists of an attenuator stage followed by a fixed-gain amplifier to provide voltage gain control from –6 dB to 26 dB in 1-dB steps (as shown in the Functional Block Diagram section) with an overall 32-dB gain range. The variable gain control for the device is offered through the digital serial peripheral interface (SPI) register. The device has a unique attenuator ladder architecture providing dynamic range improvements where the overall noise figure (NF) remains relatively constant for the first 5-dB attenuator steps, with NF degrading proportional to the attenuator steps on the sixth step. This behavior repeats over the entire gain range; see Figure 26.
The device has a differential input impedance of 100-Ω and is intended to be driven differentially by a matched 100-Ω differential source impedance for the best linearity and noise performance. The LMH6401 has two on-chip, 10-Ω resistors, one on each output (as shown in the Functional Block Diagram section). For most load conditions, the 10-Ω resistors are only a partial termination. Consequently, external termination resistors are required in most applications. See Table 11 for common load values and the matching resistors.
The LMH6401 supports a common-mode reference input (VOCM) pin to align the amplifier output common-mode with the subsequent stage (ADC) input requirements. The output common-mode of the LMH6401 is self-biased to mid-supply when the VOCM pin is not driven externally. The device can be operated on a power-supply voltage range of 4.0 V to 5.25 V and supports both single- and split-supply operation. For correct digital operation, the positive supply must not be below 2 V for ground reference logic. A power-down feature is also available through the SPI register and the external PD pin.
9.4 Device Functional Modes
9.4.1 Power-On Reset (POR)
The LMH6401 has a built-in, power-on reset (POR) that sets the device registers to their default state (see Table 3) on power-up. Note that the LMH6401 register information is lost each time power is removed. When power is reapplied, the POR ensures the device enters a default state. Power glitches (of sufficient duration) can also initiate the POR and return the device to a default state.
9.4.2 Power-Down (PD)
The device supports power-down control using an external power-down (PD) pin or by writing a logic high to bit 6 of SPI register 2h (see the Register Maps section). The external PD is an active high pin. When left floating, the device defaults to an on condition when the PD pin defaults to logic low as a result of the internal pulldown resistor. The device PD thresholds are noted in the Electrical Characteristics table. The device consumes approximately 7 mA in power-down mode. Note that the SPI register contents are preserved in power-down mode.
9.4.4 Gain Control
The LMH6401 gain can be controlled from 26-dB gain (0-dB attenuation) to –6-dB gain in 1-dB steps by digitally programming the SPI register 2h. See the Register Maps section for more details.
9.5.1 Details of the Serial Interface
The LMH6401 has a set of internal registers that can be accessed by the serial interface controlled by the CS (chip select), SCLK (serial interface clock), SDI (serial interface input data), and SDO (serial interface readback data) pins. Serial input to the device is enabled when CS is low. SDI serial data are latched at every SCLK rising edge when CS is active (low). Serial data are loaded into the register at every 16th SCLK rising edge when CS is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active CS pulse. The first eight bits form the register address and the remaining eight bits form the register data. The interface can function with SCLK frequencies from 50 MHz down to very low speeds (of a few Hertz) and also with a non-50% SCLK duty cycle. A summary of the LMH6401 SPI protocol follows:
- SPI-1.1 compliant interface
- SPI register contents protected in power-down
- SPI-controlled power-down
- Powered from the main VS+ power supply
- 1.8-V logic compliant