Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.
|Part number||Order||Input level||Number of outputs||Output frequency (Max) (MHz)||Output level||Operating temperature range (C)||Features||VCC out (V)||VCC core (V)||Programmability|
|4||800||LVPECL||-40 to 85||Integrated Integer-N PLL||3.3||3.3||uWire|
|LMK02000||Samples not available||
|8||800||LVDS||-40 to 85||Integrated Integer-N PLL||3.3||3.3||uWire|