Product details

Function Cascaded PLLs Number of outputs 6 RMS jitter (fs) 150 Output frequency (min) (MHz) 0.35 Output frequency (max) (MHz) 1570 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Features Integrated VCO Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Cascaded PLLs Number of outputs 6 RMS jitter (fs) 150 Output frequency (min) (MHz) 0.35 Output frequency (max) (MHz) 1570 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Features Integrated VCO Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
WQFN (RHS) 48 49 mm² 7 x 7

  • Cascaded PLLatinum PLL Architecture
  • PLL1
  • Phase detector rate of up to 40 MHz
  • Integrated Low-Noise Crystal Oscillator Circuit
  • Dual redundant input reference clock with LOS
  • PLL2
  • Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
  • Phase detector rate up to 100 MHz
  • Input frequency-doubler
  • Integrated Low-Noise VCO
  • Ultra-Low RMS Jitter Performance
  • 150 fs RMS jitter (12 kHz – 20 MHz)
  • 200 fs RMS jitter (100 Hz – 20 MHz)
  • LVPECL/2VPECL, LVDS, and LVCMOS outputs
  • Support clock rates up to 1080 MHz
  • Default Clock Output (CLKout2) at power up
  • Five dedicated channel divider and delay blocks
  • Pin compatible family of clocking devices
  • Industrial Temperature Range: -40 to 85 °C
  • 3.15 V to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

  • Target Applications

  • Data Converter Clocking
  • Wireless Infrastructure
  • Networking, SONET/SDH, DSLAM
  • Medical
  • Military / Aerospace
  • Test and Measurement
  • Video

  • Cascaded PLLatinum PLL Architecture
  • PLL1
  • Phase detector rate of up to 40 MHz
  • Integrated Low-Noise Crystal Oscillator Circuit
  • Dual redundant input reference clock with LOS
  • PLL2
  • Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
  • Phase detector rate up to 100 MHz
  • Input frequency-doubler
  • Integrated Low-Noise VCO
  • Ultra-Low RMS Jitter Performance
  • 150 fs RMS jitter (12 kHz – 20 MHz)
  • 200 fs RMS jitter (100 Hz – 20 MHz)
  • LVPECL/2VPECL, LVDS, and LVCMOS outputs
  • Support clock rates up to 1080 MHz
  • Default Clock Output (CLKout2) at power up
  • Five dedicated channel divider and delay blocks
  • Pin compatible family of clocking devices
  • Industrial Temperature Range: -40 to 85 °C
  • 3.15 V to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

  • Target Applications

  • Data Converter Clocking
  • Wireless Infrastructure
  • Networking, SONET/SDH, DSLAM
  • Medical
  • Military / Aerospace
  • Test and Measurement
  • Video

  • The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

    The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

    The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.


    The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

    The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

    The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.


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    Technical documentation

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    Type Title Date
    * Data sheet LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs datasheet (Rev. J) 19 Sep 2011
    User guide LMK040xx Evaluation Board User's Guide (Rev. B) 08 Jan 2015
    Application note AN-1910 LMK04000 Family Phase Noise Characterization (Rev. A) 26 Apr 2013
    Application note AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) 26 Apr 2013
    EVM User's guide AN-1942 LMH6517 Evaluation Board (Rev. B) 26 Apr 2013
    Application note AN-1950 Silently Powering Low Noise Applications (Rev. A) 22 Apr 2013
    User guide High-IF Sub-sampling Receiver Subsystem User Guide 27 Jan 2012
    User guide SP16130CH4RB Low IF Receiver Reference Design User Guide 27 Jan 2012
    Design guide Clock Conditioner Owner's Manual 10 Nov 2006

    Design & development

    For additional terms or required resources, click any title below to view the detail page where available.

    Evaluation board

    LMK04031BEVAL — Clock Jitter Cleaner With Cascaded PLLs and Integrated 1.5 GHz VCO (LVPECL LVDS LVCMOS Outputs)

    The LMK04031 is a precision low noise programmable jitter cleaner, clock multiplier, and distribution device. The LMK04031, with two internal PLLs and an extremely high performance internal LC voltage controlled oscillator (VCO), can be combined with a low cost VCXO module or an external crystal (...)

    User guide: PDF
    Not available on TI.com
    Software programming tool

    CODELOADER CodeLoader Device Register Programming v4.19.0

    The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

    Which software do I use?

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    Supported products & hardware

    Supported products & hardware

    Products
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    RF PLLs & synthesizers
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    Clock jitter cleaners & synchronizers
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    Clock buffers
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    Hardware development
    Evaluation board
    LMK00301EVAL LMK00301 Evaluation Board LMK01000EVAL 1.6 GHz Low Noise Clock Buffer, Divider, and Distributor LMK03000CEVAL Precision Clock Conditioner with Integrated VCO (1185 - 1296 MHz) LMK03001CEVAL Precision Clock Conditioner with Integrated VCO (1470 - 1570 MHz) LMK03002CEVAL Precision Clock Conditioner with Integrated VCO (1566 - 1724 MHz) LMK03033CEVAL Precision Clock Conditioner with Integrated VCO (1843 - 2160 MHz) LMK03200EVAL LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO Evaluation Board LMK03806BEVAL LMK03806B Evaluation Board LMK04000BEVAL Clock Jitter Cleaner With Cascaded PLLs and Integrated 1.2 GHz VCO (LVPECL LVCMOS Outputs) LMX25311226EVAL High Performance Frequency Synthesizer System with Integrated VCO (592 - 634 MHz, 1184 - 1268 MHz)
    Support software

    CLOCKDESIGNTOOL Clock Design Tool Software

    The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

    Supported products & hardware

    Supported products & hardware

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    RF PLLs & synthesizers
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    Simulation model

    LMK04031 IBIS Model

    SNOM112.ZIP (58 KB) - IBIS Model
    Simulation tool

    PSPICE-FOR-TI — PSpice® for TI design and simulation tool

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    WQFN (RHS) 48 View options

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