LMK04610 Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual PLLs | TI.com

LMK04610
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Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual PLLs

 

Description

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.

Features

  • Dual-loop PLL architecture
  • Ultra low noise (10 kHz to 20 MHz):
    • 48-fs RMS jitter at 1966.08 MHz
    • 50-fs RMS jitter at 983.04 MHz
    • 61-fs RMS jitter at 122.88 MHz
  • –165-dBc/Hz noise floor at 122.88 MHz
  • JESD204B support
    • Single shot, pulsed, and continuous SYSREF
  • 10 differential output clocks in 8 frequency groups
    • Programmable output swing between 700 mVpp to 1600 mVpp
    • Each output pair can be configured to SYSREF clock output
    • 16-bit channel divider
    • Minimum SYSREF frequency of 25 kHz
    • Maximum output frequency of 2 GHz
    • Precision digital delay, dynamically adjustable
      • Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
    • 60-ps step analog delay
    • 50% duty cycle output divides, 1 to 65535
      (even and odd)
  • Two reference inputs
    • Holdover mode, when inputs are lost
    • Automatic and manual switch-over modes
    • Loss-of-signal (LOS) detection
  • 0.88-W typical power consumption with 10 outputs active
  • Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
  • Fully integrated programmable loop filter
  • PLL2
    • PLL2 phase detector rate up to 250 MHz
    • OSCin frequency-doubler
    • Integrated low-noise VCO
  • Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
  • 3- or 4-wire SPI interface (4-wire is default)
  • –40ºC to +85ºC industrial ambient temperature
  • Supports 105ºC PCB temperature (measured at thermal pad)
  • LMK04610: 8-mm × 8-mm VQFN-56 package with 0.5-mm pitch

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WEBENCH® Designer LMK04610

Recommend Input Frequency Output Frequencies
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Parametrics

Compare all products in Clock jitter cleaners & synchronizers Email Download to Excel
Part number Order Function Number of outputs Output frequency (Min) (MHz) Output frequency (Max) (MHz) Supply voltage (Min) (V) RMS jitter Supply voltage (Max) (V) Input type Output type Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG) Number of Inputs
LMK04610 Order now Single-loop PLL     10     0.03     2000     1.7     0.065     3.465     LVCMOS
LVDS
LVPECL    
LVDS
LVPECL    
Catalog     -40 to 85     QFN | 56     56QFN: 64 mm2: 8 x 8 (QFN | 56)     2    
LMK04208 Order now Single-loop PLL     7     0.329     3072     3.15     0.111     3.45     LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
Catalog     -40 to 85     WQFN | 64     64WQFN: 81 mm2: 9 x 9 (WQFN | 64)     2    
LMK04616 Order now Single-loop PLL     16     0.03     2000     1.7     0.065     3.465     LVCMOS
LVDS
LVPECL    
LVDS
LVPECL    
Catalog     -40 to 85     NFBGA | 144     144NFBGA: 100 mm2: 10 x 10 (NFBGA | 144)     4    
LMK04808 Order now Dual-loop PLL     14     0.22     3072     3.15     0.111     3.45     LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
Catalog     -40 to 85     WQFN | 64     64WQFN: 81 mm2: 9 x 9 (WQFN | 64)     2    
LMK04821 Order now Single-loop PLL     15     0.045     2075     3.15     0.091     3.45       LVCMOS
LVDS
LVPECL    
Catalog     -40 to 85     WQFN | 64     64WQFN: 81 mm2: 9 x 9 (WQFN | 64)     3