LMK04610 Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual PLLs | TI.com

LMK04610 (ACTIVE) Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual PLLs

 

Description

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.

Features

  • Dual Loop PLL Architecture
    • 65-fs RMS Jitter (10 kHz to 20 MHz)
    • 85-fs RMS Jitter (100 Hz to 20 MHz)
    • –165-dBc/Hz Noise Floor at 122.88 MHz
  • JESD204B Support
    • Single Shot, Pulsed, and Continuous SYSREF
  • 10 Differential Output Clocks in 8 Frequency Groups
    • Programmable Output Swing Between 700 mVpp to 1600 mVpp
    • Each Output Pair Can be Configured to SYSREF Clock Output
    • 16-Bit Channel Divider
    • Minimum SYSREF Frequency of 25 kHz
    • Maximum Output Frequency of 2 GHz
    • Precision Digital Delay, Dynamically Adjustable
      • Digital Delay (DDLY) of ½ × Clock Distribution Path Frequency (2 GHz Maximum)
    • 60-ps Step Analog Delay
    • 50% Duty Cycle Output Divides, 1 to 65535
      (Even and Odd)
  • 2 Reference Inputs
    • Holdover Mode, When Inputs are Lost
    • Automatic and Manual Switch-Over Modes
    • Loss-of-Signal (LOS) Detection
  • 0.88-W Typical Power Consumption With 10 Outputs Active
  • Operates Typically From a 1.8-V (Outputs, Inputs) and 3.3-V Supply (Digital, PLL1, PLL2_OSC, PLL2 Core)
  • Fully Integrated Programmable Loop Filter
  • PLL2
    • PLL2 Phase Detector Rate Up to 250 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO
  • Internal Power Conditioning: Better Than –80dBc PSRR on VDDO for 122.88-MHz Differential Outputs
  • 3- or 4-Wire SPI Interface (4-Wire is Default)
  • –40ºC to +85ºC Industrial Ambient Temperature
  • Supports 105ºC PCB Temperature (Measured at Thermal Pad)
  • LMK04610: 8-mm × 8-mm VQFN-56 Package With 0.5-mm Pitch

All trademarks are the property of their respective owners.

WEBENCH® Designer LMK04610

Recommend Input Frequency Output Frequencies
 MHz
Input Frequency  MHz
 MHz  MHz

Parametrics

Compare all products in Dual/cascaded PLL Email Download to Excel
Part number Order Number of outputs Output level Output frequency (Min) (MHz) Output frequency (Max) (MHz) Number of Inputs Input level RMS jitter VCO frequency (Min) (MHz) VCO frequency (Max) (MHz) Supply voltage (Min) (V) Supply voltage (Max) (V) Features Operating temperature range (C)
LMK04610 Order now 10     HCSL
HSDS
LVDS
LVPECL    
0.03     2000     2     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.065     5800     6200     1.7     3.465     105C PCB temp
Holdover mode
JESD204B SYSREF
JESD204B SYSREF Generation
Jitter Cleaner/Clock Generator/Clock Distribution
Integrated LDOs
Integrated Loop Filters
Low Power Design
Manual and automatic switching between inputs
Semi-Digital PLL
SPI    
-40 to 85    
LMK04208 Order now 7     LVCMOS
LVDS
LVPECL    
0.329     3072     2     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.111     2750     3072     3.15     3.45     Holdover mode
Int. xtal oscillator
Manual/auto switch
SPI
uWire    
-40 to 85    
LMK04616 Order now 16     HCSL
HSDS
LVDS
LVPECL    
0.03     2000     4     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.065     5800     6200     1.7     3.465     105C PCB temp
Holdover mode
JESD204B SYSREF
JESD204B SYSREF Generation
Jitter Cleaner/Clock Generator/Clock Distribution
Integrated LDOs
Integrated Loop Filters
Low Power Design
Manual and automatic switching between inputs
Semi-Digital PLL
SPI    
-40 to 85    
LMK04808 Order now 14     LVCMOS
LVDS
LVPECL    
0.22     3072     2     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.111     2750     3072     3.15     3.45     uWire
SPI
Holdover mode
Manual/auto switch
Int. xtal oscillator    
-40 to 85    
LMK04821 Order now 15     HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.045     2075     3     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.091     365     2075     3.15     3.45     105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
-40 to 85